AN/FSQ-32
| Company type | Military computer project |
|---|---|
| Industry | Defense electronics, Computer hardware |
| Predecessor | AN/FSQ-7 |
| Founded | 1956 |
| Headquarters | Santa Monica , United States |
| Products | Transistor-based solid-state computers for air defense and air traffic control |
The AN/FSQ-32 SAGE Solid State Computer—originally designated AN/FSQ-7A until December 1958 and informally known as the "Q-32"—was a military computer project initiated by the United States Air Force for installation within Super Combat Centers, which were housed in nuclear bunkers and select surface-level military installations. In 1958, the Air Defense Command planned to procure 13 Q-32 central units to support various Air Divisions and Sectors.
According to the Joint Electronics Type Designation System (JETDS), the label "AN/FSQ-32" identifies this as the 32nd iteration of an Army-Navy fixed special combination electronic system. This naming convention remains in use for all electronic systems developed by the Department of Defense.
Background
In 1956, IBM was commissioned by the Air Research and Development Command to create a transistor-based, solid-state computer. Officially unveiled in June 1958, this "SAGE Solid State Computer" was projected to deliver computing power approximately seven times greater than that of the AN/FSQ-7. By November 1958, ADC aimed to deploy 13 solid-state AN/FSQ-7A units by April 1964, each capable of integrating data from up to 20 long-range radar sources across an operational area exceeding 1,000 miles in all directions. These systems processed low-speed Teletype inputs transmitted over 32 telephone lines.
On November 17, 1958, NORAD opted to pursue acquisition of the solid-state computer alongside reinforced facilities, leading to the cancellation of remaining vacuum-tube AN/FSQ-8 centrals intended for combat centers (with one unit converted into an AN/FSQ-7).
The AN/FSQ-32 computers were designed to fulfill several roles: 1. Managing combat center functions as replacements for vacuum-tube AN/FSQ-8 systems, 2. Linking radar and weapons systems for weapons direction—including backup guidance for CIM-10 Bomarc missiles or manned interceptor Ground-Control Intercept (GCI) if above-ground Direction Centers became inoperative, and 3. Supporting air traffic control operations.
Following a 1958 agreement among the USAF, Civil Aeronautics Administration (CAA), and Airways Modernization Board, plans were made to colocate air route traffic control centers with air defense installations to share radar assets at SAGE sites. A subsequent agreement in 1959 designated air traffic control facilities within hardened structures at nine U.S. Super Combat Centers, aligning Air Defense Sectors with FAA regions to enhance coordination under the new SAGE Implementation Schedule.
Nevertheless, on December 21, 1959, the Office of Defense Research and Engineering ordered a cessation of AN/FSQ-32 production. By January 1960, the Secretary of Defense recommended terminating the SCC program altogether; this cancellation was finalized by March 18, 1960. The associated SAGE Air Traffic Integration (SATIN) initiative was also discontinued. Instead, Back-Up Interceptor Control capabilities were established using smaller solid-state computers installed at above-ground SAGE radar stations to improve system survivability.
The intended deployment sites for AN/FSQ-32 units included sectors such as Ottawa, St. Louis, San Antonio, Raleigh, Syracuse, Chicago, Spokane, Minot, Portland, Phoenix, Miami (above-ground), Albuquerque (above-ground), and Shreveport (above-ground). After boundary adjustments in 1959 eliminated Shreveport and reclassified several sectors, deployment plans were reduced to 12 locations.
Prototype
The AN/FSQ-32 prototype represented the largest transistorized computer constructed at the time, initially weighing , and ultimately increasing to with 18 tape drives and 10 storage units installed. This mainframe was housed at the System Development Corporation (SDC) headquarters located in Santa Monica, California, where SDC developed its software utilizing JOVIAL. Occupying nearly an entire floor of the facility, the system demanded extensive cooling infrastructure.
ARPA research
During the early 1960s, the prototype was transferred to the Advanced Research Projects Agency (ARPA), remaining stationed in Santa Monica and serving as a foundation for ARPA's Information Processing Techniques Office. SDC investigated the potential for the prototype to manage multiple batch jobs concurrently ("time-sharing") and to support users distributed across different locations.
On April 23, 1963, Dr. J. C. R. Licklider, then ARPA Director of Behavioral Sciences Command & Control Research, emphasized initial difficulties in creating a time-sharing computer network using existing software tools. One of the earliest remote users of the prototype was the Augmentation Research Center at the Stanford Research Institute.
Time-sharing
By June 1963, the Time-Sharing System (TSS) Model Zero was demonstrated with magnetic drums added to facilitate time-sharing capabilities. Each user was allocated a priority-based time slice measured in milliseconds, during which their program was transferred from magnetic drums into faster-access memory for execution before being saved back with any modifications. This design drew inspiration from pioneering work at Bolt, Beranek, and Newman and MIT's CTSS. User terminals included several Teletype Model 33 ASRs.
Computer network
Following the SAGE Sector Warning Network established for the initial operational SAGE direction center, recognized as the first functional computer network, Lincoln Labs in October 1965 connected a TX-2 solid-state computer to the Q-32 prototype to send the inaugural telecommunication of time packets.
Description
The prototype functioned as an IBM 4020 Military Computer comprising a central processing unit, memory modules, both High-Speed and Low-Speed Input/Output systems, and an Operations Console designed for operational control and maintenance tasks. The AN/FSQ-32 central system was intended to include additional display and console units for use by personnel from Air Defense Command, Army Air Defense Command, Federal Aviation Administration, and other agencies at SCC/DCs. It supported consoles dedicated to weapons direction for dispatching and guiding manned interceptors, controlling launch and guidance of CIM-10 Bomarc missiles, as well as launching Nike surface-to-air missile systems.
Central processing unit
The machine's Instruction set employed a fixed single-word length consisting of 24 bits allocated to operation codes and another 24 bits assigned to addressing. The address field comprised 18 bits dedicated to memory locations along with bits reserved for index registers and indirect addressing modes. The operation segment contained both opcode and modifiers that allowed operations targeting specific bytes or bits without requiring masking procedures. Certain modifiers enabled the 48-bit ALU to process paired 24-bit operands simultaneously for vector processing tasks. CPU controls incorporated sense switches for software interaction, a run/halt toggle switch, and an audio assembly capable of manipulating accumulator bits to produce tones or musical sounds.
Memory
The memory architecture utilized a word-addressable scheme with 48-bit words, each segmented into eight 6-bit bytes—an arrangement typical of scientific computers from that era, such as those by IBM. The addressing capacity extended to 256K words; the initial model featured 128K words (48 bits plus two parity bits) and was cooled using a combination of oil and water. The memory system incorporated four switch banks, each with 48 positions, designed for storing brief programs, alongside a plug panel capable of holding 32 words, functioning as an elementary form of ROM for bootstrap or diagnostic routines. The memory operated with a cycle time of 2.5 microseconds. Nevertheless, the absence of memory management restricted the system’s overall functionality.
Input/Output
High-Speed Input/Output interfaced directly with the Drum Memory subsystem, which included a control unit and a pair of vertical drum devices. Each drum was capable of reading and writing 50 bits simultaneously, facilitating fast data throughput. The memory was divided into 17 segments containing 8,192 words each, culminating in a total storage capacity of 139,264 words. Operating at 208 VAC and 45 Hz, the drums required a motor generator to convert from the standard 60 Hz power supply, resulting in increased noise output. Additionally, HSIO connected with the SACCS EDTCC to enable expanded SACCS integration.
Low-Speed Input/Output accommodated various peripherals:
- Communications Multiplexor
- Two Tape Controllers linked to sixteen IBM 729-V Tape Drives
- A Disk File Controller (a modified Tape Controller) managing a Bryant Disk File consisting of 25 disks (39 inches in diameter), equipped with 125 hydraulically controlled read/write heads and offering 26 megabyte capacity
- An IBM 1401, responsible for handling data from unit-record devices including the IBM 1402 Card Reader/Punch, IBM 1403 Line Printer, and two IBM 729-V Tape Drives
- Two IBM Selectric Typewriters utilized for operational communications, diagnostics, and maintenance activities
Notes
- The AN/FSQ-32 designated for the "Canadian" 35th Air Division within the Ottawa Air Defense Sector was intended to run only the "DC program". The three systems planned for Albuquerque, Miami, and Shreveport were meant exclusively as Direction Centers rather than Super Combat Centers or SCC/DCs.