Chipkill
| Industry | Computer hardware |
|---|---|
| Founded | June 16, 1911 in Endicott, New York, United States |
| Founder | Charles Ranlett Flint |
| Headquarters | Armonk , United States |
| Products | Computer hardware, including Chipkill technology |
| Website | www |
Chipkill is IBM’s proprietary technology for sophisticated error detection and correction (ECC) in computer memory systems, designed to safeguard against failures of individual chips as well as multiple bit errors within a single chip. One method involves distributing the bits of a Hamming code ECC word across several chips, ensuring that the failure of one chip impacts only a single ECC bit per word, enabling data recovery even if an entire chip fails. More complex coding schemes, such as BCH codes, allow correction of multiple bit errors with reduced overhead.
Frequently, Chipkill is combined with dynamic bit-steering, which swaps out defective chips for spares once error thresholds are surpassed. This mechanism resembles RAID protection used for disk drives but is applied to memory hardware. Created by IBM Corporation during the 1990s, Chipkill is an essential feature in Reliability, Availability, and Serviceability (RAS) implementations, primarily utilized in SSDs, mainframe computers, and midrange server platforms.
Comparable solutions include Sun Microsystems’ Extended ECC, HP’s Advanced ECC and Chipspare, as well as Intel’s Lockstep memory, which provides double-device data correction (DDDC). Similar protective technologies for SSDs are offered by Micron under the name redundant array of independent NAND (RAIN) and by SandForce as RAISE level 2.
Research from 2009 analyzing Google’s data center revealed that DRAM errors tend to recur at identical locations, with approximately 8% of DIMMs experiencing errors annually. More than 85% of correctable errors were followed by additional errors within the same month. DIMMs equipped with Chipkill demonstrated significantly fewer uncorrectable errors compared to those using standard single-bit ECC. A 2010 study conducted by the University of Rochester further validated that Chipkill memory substantially decreases error rates through analysis of real-world data and simulation models.
See also
- ECC memory
- Lockstep memory
- Memory ProteXion
- Redundant array of independent memory
- Single-error correction and double-error detection (SECDED)
External links
- Intel E7500 Chipset MCH Intelx4 Single Device Data Correction (x4 SDDC) Implementation and Validation, Intel Application Note AP-726, August 2002
- DRAM study challenges assumptions about errors, Ars Technica, October 7, 2009
- Enabling Memory Reliability, Availability, and Serviceability on Dell PowerEdge Servers, 2005
- Chipkill correct memory architecture, August 2000, by David Locklear
- The Mathematics of Chipkill ECC, October 2015, by Bob Day