Cray XMT
| Industry | Supercomputing |
|---|---|
| Headquarters | United States |
| Products | Cray XMT, Cray XMT2 |
Cray XMT (short for Cray eXtreme MultiThreading, previously codenamed Eldorado) represents a scalable, multithreaded shared memory supercomputer design developed by Cray. It builds upon the third iteration of the Tera MTA architecture and is specifically engineered for handling extensive graph-related challenges, including semantic databases, large-scale data analytics, and pattern recognition. Launched in 2005, this model replaced the earlier Cray MTA-2 by reducing manufacturing expenses through the integration of standard components and pre-existing subsystems. The Cray XMT delivered substantial performance enhancements, nearly tripling peak capabilities, supporting configurations with up to 8,192 processors and 128 terabytes of memory, along with a data TLB capable of addressing as much as 512 terabytes.
The architecture utilizes a scrambled content-addressable memory approach on DDR1 ECC modules to evenly distribute memory access across its unified global address space. It incorporates four Extended Memory Semantics bits per 64-bit word to facilitate precise synchronization directly within memory locations. Instead of relying on the operating system, hardware thread allocation is managed by specific instructions, and the system operates without hardware interrupts.
Front-end service nodes operate on AMD Opteron CPUs running SUSE Linux Enterprise, while the back-end compute nodes are powered by Threadstorm3 processors executing MTK, a microkernel derived from BSD. Communication between these front-end and back-end components is handled via the Lightweight User Communication (LUC) interface, which functions as a bidirectional RPC-style client/server protocol.
Threadstorm3
Threadstorm3—previously referred to as the "MT processor" and simply Threadstorm before the XMT2 iteration—is a 64-bit single-core VLIW barrel processor compatible with the 940-pin Socket 940 used by AMD Opteron chips. It supports 128 hardware streams, each corresponding to a software thread, effectively enabling 128 hardware threads per CPU. Operating at a clock speed of 500 MHz, it executes instructions based on the MTA instruction set or its extended version. The processor includes a 128KB data buffer with 4-way set associativity and maintains 128 independent register sets and program counters—one for each stream—that are swapped every cycle. Its theoretical peak performance reaches approximately 1.5 GFLOPS.
The Threadstorm3 processor integrates three functional units—memory access, fused multiply-add, and control—that function simultaneously within a single cycle. Each stream contains 32 general-purpose registers, eight target registers, and a status word including its program counter. Control over job distribution among threads is minimal. Its pipeline spans 21 cycles, ensuring that instructions for any given stream are issued no more frequently than every 21 cycles. The processor’s Thermal Design Power (TDP) is rated at 30 watts.
Owing to its design featuring thread-level context switching every cycle, Threadstorm3 avoids performance degradation caused by memory latency. At each clock tick, one thread executes an instruction while another issues a memory request, assuming data returns before that thread’s next turn. This mechanism contrasts sharply with traditional architectures that stall during memory access delays and excels in processing irregular data traversal tasks that defy conventional caching strategies. Burton J. Smith served as the lead architect responsible for Threadstorm’s design.
Cray XMT2
The Cray XMT2—also known as the "next-generation XMT" or simply XMT—is a scalable, multithreaded shared memory supercomputer developed by Cray. It builds upon the fourth iteration of the Tera MTA architecture and was launched in 2011 as the successor to the original Cray XMT. This model resolves previous challenges related to memory hotspots. The system integrates Threadstorm4 processors within Cray XT5 blade enclosures, expanding memory capacity eight times to 512 TB and enhancing memory bandwidth threefold to 300 MHz by doubling the number of memory modules per node and utilizing DDR2 technology. Innovations in XMT2 include the introduction of Node Pair Link connections between Threadstorm units and dedicated memory-only nodes. The Threadstorm4 processor packages deactivate CPU cores and disable HyperTransport 1.x components. While preserving the scrambled content-addressable memory scheme from its predecessor, XMT2 modifies the extended memory state bits to use two EMS bits (full/empty and extended) instead of four.
Threadstorm4
Threadstorm4—also referred to as "Threadstorm IV" or "Threadstorm 4.0"—is a 64-bit single-core VLIW barrel processor designed for compatibility with the 1207-pin Socket F used by AMD Opteron CPUs. It maintains support for 128 hardware threads, consistent with its predecessor Threadstorm3, but features an upgraded DDR2-compatible memory controller and adds eight extra trap registers per thread. Cray deliberately chose not to implement DDR3 support despite its higher speeds, favoring existing Cray XT5 infrastructure and minimizing power consumption. The longer burst length of DDR3 would have introduced greater overhead for XMT2’s characteristic random 8-byte memory accesses, making DDR2 a more efficient choice.
Scorpio
In the development phase following XMT, Cray investigated a multi-core version of Threadstorm3 named Scorpio. This design preserved essential elements such as multiplexed hardware threading and extended state bits per 64-bit memory word. However, the Scorpio initiative was discontinued before any chips were fabricated.
Future
After the release of XMT2, further advancement of Threadstorm4 and the MTA architecture ceased quietly, likely influenced by competition from mainstream processors like Intel's Xeon and possibly Xeon Phi. Although Cray never officially declared an end to the XMT or XMT2 product lines, all related customer documentation had been removed from Cray’s online resources by 2020.
Users
The Cray XMT2 found adoption in federal research laboratories, academic centers, and select commercial high-performance computing clients such as the CSCS, which operated a system equipped with 64 Threadstorm4 processors and 2 TB of global memory, as well as Noblis CAHPC. By 2020, most installations of both XMT and XMT2 had been retired.