HP Saturn

Saturn (microprocessor)
Company type	Microprocessor series
Industry	Semiconductor
Predecessor	Nut processor line
Founded	1980s
Founder	Hewlett-Packard
Area served	Hewlett-Packard calculators and handheld computers
Products	4-bit microprocessors
Parent	Hewlett-Packard

The Saturn series comprises 4-bit (datapath) microprocessors created by Hewlett-Packard during the 1980s. These processors first appeared in the HP-71B handheld computer launched in 1984 and subsequently powered a range of HP calculators, beginning with the HP-18C. This family followed the Nut processor line. The HP48SX and HP48S were the final calculator models to utilize Saturn processors produced directly by HP; later versions switched to chips manufactured by NEC. The HP 49 series initially incorporated Saturn CPUs until NEC halted production in 2003. Starting with the HP 49g+, HP adopted a Samsung S3C2410 processor featuring an ARM920T core (ARMv4T architecture), which ran a software-based Saturn hardware emulator.

The year 2000 saw the release of the HP 39G and HP 40G, marking the last calculators equipped with genuine NEC-made Saturn hardware. Subsequent devices such as the HP 39gs, HP 40gs, and HP 50g (introduced up to 2007) utilized this ARM-driven Saturn emulation. Production of the HP 50g ended in 2015 after Samsung discontinued its ARM processor line, effectively concluding the era of Saturn-based calculators.

Architecture

The Saturn processor employs a nibble-oriented serial architecture, distinguishing it from its bit-serial predecessor, the Nut. Internally, it features four separate 4-bit data buses, enabling nearly single-cycle processing for each nibble. Typically, one or two buses serve as data sources while one or two act as destinations. The smallest addressable unit is a 4-bit nibble, which encodes a single binary-coded decimal (BCD) digit. Data sizes larger than a nibble—up to 64 bits—are handled sequentially on a nibble-by-nibble basis.

This architecture supports a 64-bit internal register width and utilizes 20-bit addressing with nibble-level granularity. Its ALU instructions accommodate variable data widths ranging from one to sixteen nibbles. While early Saturn CPUs featured a 4-bit external data bus, later System on Chip (SoC) designs upgraded this to an 8-bit external data bus along with a 19-bit external address bus.

The CPU contains four 64-bit General Purpose Registers (GPRs)—named A, B, C, and D—and five additional 64-bit scratch registers (R0 through R4) dedicated solely to data storage. To perform ALU operations on scratch registers, data must first be transferred into a GPR. Other registers include a single-nibble pointer register P for nibble alignment or selection; two 20-bit data pointer registers D0 and D1 responsible for memory access; and a program counter (PC) that interoperates with GPRs. The design also incorporates an eight-level circular Last-In-First-Out (LIFO) hardware return stack (RSTK), a 16-bit software status register (ST), and a one-nibble hardware status register (HS) that holds the sticky bit flag. Input/output management is handled through a 12-bit OUT register and a 16-bit IN register used in Yorke and Clarke SoCs for keyboard scanning and beeper control, alongside a single-bit carry flag.

The interrupt mechanism is straightforward and non-prioritized: upon receiving an interrupt signal, the CPU completes its current instruction, saves the program counter onto RSTK, then jumps to address 0x0000Fh. Additionally, it interfaces directly with keyboard scanning logic.

General-purpose registers allow access to fields aligned on nibble boundaries, whereas scratch registers are limited to load/store functions only. Notable fields include W (entire 64-bit GPR), A (address field covering the first five nibbles), S (mantissa sign), XS (exponent sign), M (mantissa digits), X (exponent), B (first byte), P (nibble selected via P register), and WP (nibbles from zero through P). Registers store floating-point numbers in BCD format composed of a sign nibble ("9" indicating negative), twelve mantissa digits, and a three-digit exponent expressed in ten's complement form (±499). This BCD representation prevents rounding errors commonly encountered during binary-to-decimal conversions, which is essential for calculator precision.

Instruction and data addresses operate on nibble units with three pointer registers—including the PC—and address registers that are each 20 bits wide, enabling access to approximately one million nibbles (512 KB). Devices requiring larger memory capacities, such as the HP 48GX, implement bank switching techniques.

Originally, the Saturn CPU existed as an independent chip found in products like the HP-71B handheld and HP-28C calculator. Later models—including the HP 48S/SX, HP-28S, HP-27S, HP-42S, HP-32SII, and HP-20S—integrated the Saturn core within sophisticated System on Chip (SoC) architectures.

Example code

Below is an integer-based implementation of a BCD decimal square root algorithm using Saturn Jazz / HP Tools assembly language syntax:

** The argument is expected in A.W (less than 1E14).
** The output (integer part of the square root of A.W) will be stored in C.W:

        SETDEC
        ASL     W
        C=A     W
        A=A+A   W  
        A=A+A   W
        A=A+C   W
        ASR     W
        C=0     W
        P=      13
        LC(1)   5      
-       CSR     WP
        C=C-1   P  
--      C=C+1   P  
        A=A-C   W  
        GONC    --                  
        A=A+C   W  
        CSR     W  
        P=P-1                   
        P=P-1           
        GONC    -
        SETHEX
        A=C     W

Chipsets and applications

The initial Saturn CPU designated the full instruction set architecture. Later processors were assigned unique code names:

ISA level	Processor code name	Calculator models	Notable characteristics
0	Saturn (1LF2)	HP-44A (prototype), HP-71B (early version, 1984)	Fundamental implementation
1	Saturn (1LK7)	HP-18C (1986), HP-28C (1987), subsequent HP-71B	640 kHz operation, extended instruction set
2	Bert (1LU7)	HP-10B (1988), HP-20S (1988), HP-21S	640 kHz clock, 10 KB ROM, 256 bytes RAM, integrated LCD driver
2	Sacajawea (1LR3)	HP-14B, HP-22S, HP-32S (1988), HP-32S+, HP-32SII (1991)	640 kHz, 16 KB ROM, 512 bytes RAM, LCD controller included
2	Lewis (1LR2)	HP-17B (1988), HP 17BII (1990), HP-19B (1988), HP 19BII (1990), HP-27S, HP-28S, HP-42S	1 MHz frequency, 64 KB ROM, LCD controller, memory management, infrared interface, 3 V CMOS technology
2	Clarke (1LT8)	HP 48SX (1990), HP 48S (1991)	Runs at 2 MHz, includes LCD and memory controllers, UART and IR support, expanded instructions
2	Yorke	HP 38G (1995), HP 38G+ (1998), HP 39G (2000), HP 40G (2000), HP 48GX, HP 48G, HP 48G+, HP 49G	Operating between 3.68 and 4 MHz; features LCD and memory controllers, UART and IR control; produced by NEC; also known as Saturn 5
?	New-Yorke	Internal prototype used for the HP 48GX	Runs at 8 MHz with LCD and memory controllers, UART and IR support; never commercially released
2	Apple series (Big Apple, Mid Apple, Little Apple)	hp 39g+ (2003), HP 39gs (2006), HP 40gs (2006), hp 49g+ (2003), hp 48gII (2003/2007), HP 50g (2006)	Emulates the Yorke CPU virtually on Samsung S3C2410 ARM920T processors with additional virtual instructions ("Saturn+")

The CPU code names are inspired by figures from the Lewis and Clark Expedition of the early nineteenth century. The virtual CPU and emulator designations reference the "New-Yorke" Saturn-based system-on-chip prototype which was never launched commercially. The names "Big Apple," "Mid Apple," and "Little Apple" are derived from this New York City-themed codename.

External links

Overview at the Museum of HP Calculators

HP Saturn

Architecture

Example code

Chipsets and applications

See also

Further reading

External links