IBM System/360 architecture

IBM System/360
Industry	Computer architecture
Founded	1964
Products	Mainframe computer systems architecture

The IBM System/360 architecture represents the architecture independent of any specific model, encompassing the entire S/360 series of mainframe computer systems. Its specifications are detailed in the IBM System/360 Principles of Operation and associated documentation. Certain variations within this architecture acted as forerunners to features later incorporated into the S/370 design or held particular significance in scientific computing; these instances are highlighted separately.

Features

IBM S/360 registers

General Registers 0-15

	Two's complement representation

Floating Point Registers 0, 2, 4 and 6

S/360 PSW

Sixteen 32-bit general-purpose registers
Four 64-bit IBM hexadecimal floating-point registers
A 64-bit Program Status Word (PSW) featuring a 24-bit instruction address field
Byte-addressable memory space up to 24 bits (16 MB)
Big-endian ordering for bytes and words
A fixed instruction set encompassing binary fixed-point arithmetic and logical operations present on all models except the IBM System/360 Model 20
- An optional commercial instruction set adds decimal arithmetic capabilities; a scientific instruction set introduces floating-point instructions
- The universal instruction set incorporates storage protection instructions standard on selected models
- The IBM System/360 Model 44 includes specialized instructions tailored for data acquisition and real-time processing, with a Commercial Instruction Set feature to emulate absent instructions
- The IBM System/360 Model 20 employs a simplified instruction set limited to eight general registers, halfword instructions, commercial instructions, and distinctive I/O commands
- The IBM System/360 Model 67 supports 32-bit addressing and dynamic address translation facilitating virtual memory

Memory

The System/360 architecture addresses memory at the granularity of 8-bit bytes, with larger data units defined as halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), and quadword (16 bytes). The architecture accommodates up to 16 MB of physical memory, while the Model 67 extends this capacity to enable virtual memory addressing up to 4 GB.

Addressing

Instructions utilize truncated addressing mode, which combines a base register—selected from fifteen general-purpose registers—with a positive displacement. This method allows versatile addressing within the defined memory range.

Data formats

This architecture specifies data representations for characters, integers, decimal numbers, and hexadecimal floating-point values as follows:

Characters are stored as individual 8-bit bytes
Integers use two's complement format in halfword or fullword sizes
Packed decimal numbers occupy between one and sixteen bytes and include a sign nibble; decimal arithmetic operations trigger exceptions if invalid digits or signs occur
Zoned decimal numbers consist of digit bits combined with zone bits per byte; the sign is indicated by the zone bits in the rightmost byte
Floating-point values are held as fullword or doubleword quantities; extended precision quadword formats are supported on certain models such as the 360/85 and 360/195

Instruction formats

Instructions vary in length, being either two, four, or six bytes, with the opcode located in the first byte. The formats include:

RR (two bytes): contains either two register identifiers or a single immediate value
RS (four bytes): comprises two registers along with a base register and displacement
RX (four bytes): includes a register/modifier, an index register, and a base plus displacement
SI (four bytes): consists of an immediate value combined with base and displacement
SS (six bytes): features length fields together with two sets of base plus displacement

All instructions must be aligned on boundaries of two bytes.

Program Status Word (PSW)

The Program Status Word (PSW) is a 64-bit register that governs program execution. It encompasses system masks for I/O channels, the CPU protection key, an ASCII mode indicator, machine check enable flag, wait state status, problem state flag, interruption code, instruction length code, condition code, program mask bits for overflow and underflow exceptions, as well as the address of the next instruction.

The Load Program Status Word (LPSW) instruction is privileged and is used to load the PSW to continue execution following interruptions or mode transitions. Additional privileged instructions can modify portions of the PSW without triggering interruptions.

Interruption system

The system architecture defines five distinct classes of interruptions, each assigned a priority level to determine handling order when multiple interruptions occur simultaneously:

Interruption class	Old PSW	New PSW	Priority
Input/Output	hex 38	hex 78	4
Program	hex 28	hex 68	2
Supervisor Call	hex 20	hex 60	2
External	hex 18	hex 58	3
Machine Check	hex 30	hex 70	1

For each class, there is a designated old PSW storage location where the current processor state is saved alongside an inserted interruption code. Subsequently, the new PSW is loaded to manage the interruption. Interruptions may nest according to their priority levels.

Input/Output interruption

This type of interruption occurs upon completion of channel programs or due to asynchronous device events. The device address serves as the interruption code, while the Channel Status Word records the channel status.

Program interruption

Triggered by any among up to fifteen exception types such as operation exception (invalid instruction), privileged operation exception, execute exception (nested EXECUTE), protection exception (storage key violation), addressing exception (illegal address), specification exception (invalid instruction fields or misalignment), data exception (incorrect decimal operands), overflow exceptions, division exceptions, exponent exceptions, significance exception, and floating-point division exception. Certain models support imprecise exceptions.

Supervisor Call interruption

Initiated by Supervisor Call instructions; bits from the SVC instruction are saved as the interruption code.

External interruption

Occurs due to asynchronous events including timer expirations and external signals; specific bits within the code indicate the exact cause.

Machine Check interruption

Reports hardware faults such as parity errors not covered by other interruption types; both the code and associated data vary depending on the model.

Input/Output

I/O processes are handled by dedicated processors known as channels, which operate independently from the CPU by running their own instruction sets. In smaller systems, channel microcode is integrated within the CPU, whereas larger systems employ distinct channel hardware. Each channel may comprise several subchannels, each representing individual devices or groups of devices that share resources.

There are three categories of channels:

Byte multiplexer channels, designed for slower peripherals, support simultaneous execution of multiple CCWs.
Selector channels, intended for high-speed devices, process one command at a time.
Block multiplexer channels, suitable for devices with mechanical delays, can pause and resume commands; these are optional on Models 85 and 195.

Peripheral hardware connects via control units linked to the channels. Devices are identified by a 16-bit code called "cuu," where the upper bits specify the channel and the lower bits indicate the particular device. Control units feature address capture ranges and priority levels that influence the order in which commands are selected.

To perform I/O, the Channel Address Word (CAW) must be initialized with a storage key and the address of the first CCW. The Start I/O (SIO) instruction is then issued with the device's cuu. Following this, the system waits for an I/O interruption before processing any conditions reported by the Channel Status Word (CSW).

Channel programs are sequences of linked Channel Control Words (CCWs). Completion criteria differ based on command flags and unit status. Throughout operation, channels may generate Program-Controlled Interruptions without halting command execution.

Channel status

The CSW reflects various conditions detected by either the channel or the associated device/control unit during I/O:

Program-controlled interruption status indicates progress updates.
Incorrect length signals early termination of data transfer.
Program check denotes errors such as invalid addressing.
Protection check flags storage key mismatches.
Channel data, control, or interface checks report parity or interface faults.
Chaining check identifies data loss during chaining operations.

Unit status

Status codes provided by control units or devices include:

Attention requests operator intervention.
Status modifier flags special situations like unsupported Test I/O commands or busy states.
Control unit end clears previous busy indicators.
Busy signifies that a device or control unit is currently occupied.
Channel end marks completion of data transfer.
Device end indicates readiness to accept new commands.
Unit check signals abnormal conditions requiring a Sense command.
Unit exception indicates events such as reaching end-of-file.

Channel Address Word

This contains both a storage protection key and the initial address for channel program execution.

Channel Command Word

A doubleword detailing command code, memory address, flags, and byte count for I/O operations. Command codes cover Sense, Transfer In Channel (TIC), Read/Write operations, and control commands that modify device states.

CCW flags

Flags that influence command behavior include:

Chain-Data: continues data transfer using the buffer specified in the next CCW.
Chain-Command: proceeds with executing the subsequent CCW command.
Suppress-Length-Indication: permits continuation despite count mismatches.
Skip: avoids accessing storage during command execution.
Program-Controlled Interruption: requests CPU notification while executing commands.

Channel Status Word

The Channel Status Word (CSW) delivers comprehensive information following I/O interruptions, including details such as the protection keys in use, the address of the last fetched CCW, status bits that reveal conditions detected in the unit or channel during processing, and the residual count indicating the number of bytes not transferred.

I/O Instructions

There are four privileged instructions dedicated to I/O management:

Start I/O (SIO) launches channel programs based on the settings in the CAW.
Test I/O (TIO) checks the status of a channel or device and may save the CSW.
Halt I/O (HIO) attempts to stop any currently running channel programs.
Test Channel (TCH) examines channel status without interrupting active operations or saving the CSW.

Operator Controls

While the System/360 architecture defines standard operator functions, their physical implementation can differ across various models:

Core functions comprise:

System Reset clears the processor state and cancels pending interrupts but does not reset shared I/O devices.
Initial Program Load (IPL) loads system software from designated device addresses, initiated either by operator input or automated processes.
Emergency Pull Switch immediately cuts power but risks hardware damage due to bypassing proper shutdown procedures.
Power On starts the power-up process, including system reset.
Power Off initiates a controlled shutdown that preserves storage contents, though storage keys may be lost.

Additional controls include an interrupt key that triggers external interrupts; indicator lights that reflect processor conditions such as wait or manual stop; load unit controls for selecting IPL devices; switches for choosing between continuous processing and single-step execution modes; storage-select switches determining access types; address/data switches for specifying operands during store or display operations; store/display keys for manual data manipulation; set IC key for adjusting the instruction counter; address-compare switches enabling halts on matching addresses; and an alternate-prefix light indicating when prefix triggering is active.

Byte-Aligned Operands

Certain models, such as the S/360-85, loosen alignment restrictions for some problem-state instructions without offering a way to disable this behavior.

Decimal Arithmetic

Packed decimal instructions operate on numbers composed of digits followed by a sign nibble. Invalid digits or signs cause data exceptions except within PACK and UNPACK instructions.

Direct Control

Provides six external signal lines along with an eight-bit data path linking external devices directly to storage.

Floating-Point Arithmetic

Features four floating-point registers supporting hexadecimal floating-point formats at single and double precision. Extended precision is available on specific models like the 360/85 and 360/195.

Interval Timer

When installed, this timer decrements a word at fixed intervals and generates external interrupts upon reaching zero. Timer frequency varies by model, ranging from AC power supply frequency to high-resolution timers in larger systems.

Multi-System Operation

Enables multi-processor configurations through capabilities such as Direct Control and direct address relocation, known as "prefixing."

Storage safeguards

The system employs four-bit storage keys assigned to each 2048-byte segment, which are verified during store operations initiated by either the CPU or I/O channels. A key value of zero disables this protection mechanism, whereas any nonzero key enforces access restrictions that prevent malfunctioning programs from overwriting essential operating system components or other applications' memory areas. Certain models offer an additional fetch protection feature that prohibits instruction fetches from memory blocks marked as protected.

Variations and enhancements

The IBM System/360 Model 20 deviates considerably from the standard S/360 architecture. The IBM System/360 Model44 excludes some instructions but compensates by simulating them through concealed memory, allowing it to maintain compatibility with conventional software. Various models incorporate enhancements such as emulation instructions or paging capabilities. Multiprocessing implementations differ notably between the S/360-65 multisystem mode and the incompatible modifications found in the S/360 Model67-2. Some of these variations acted as forerunners to functionalities later standardized in the IBM System/370 architecture.

References

S360

External links

Introduction to IBM System/360 Architecture (Student Text)