IBM System/370-XA
| Company type | Instruction set architecture |
|---|---|
| Industry | Computing |
| Founded | October 21, 1981 |
| Headquarters | Armonk , United States |
| Products | IBM 308X series processors |
IBM System/370-XA represents an instruction set architecture introduced by IBM on October 21, 1981, specifically for the IBM 308X series processors, with its official launch occurring in April 1983. This architecture builds upon the IBM System/370 framework by incorporating support for 31-bit virtual and physical addressing, along with a revamped input/output (I/O) system design.
31-bit virtual addressing
Within the System/360 and System/370 architectures, general-purpose registers were designed as 32-bit entities, enabling 32-bit arithmetic operations and storing addresses in 32-bit words—thus categorizing these systems as 32-bit architectures. Nevertheless, apart from the 360/67, these systems effectively utilized only 24 bits for addressing by disregarding the uppermost 8 bits. This approach corresponded with the prevalent physical memory sizes during that era and was evident in instructions such as (Load Address), which cleared the highest eight bits. A significant portion of software developed for System/360 and System/370 relied on this 24-bit logical addressing scheme, so eliminating this restriction posed potential compatibility challenges.
To resolve this, a new addressing mode bit was incorporated into the Program Status Word, enabling software to operate either in the traditional 24-bit mode (where the top eight bits are ignored) or in a 31-bit mode (where only the most significant bit is disregarded). The decision to adopt 31 bits instead of a full 32 was influenced by several considerations:
- Preserving the highest-order bit as a control or escape flag, which was crucial for conventions like indicating the last parameter word in subroutine calls.
- Compatibility with loop control instructions and , which interpreted arguments as signed values; this rationale underpinned the Model 67’s adoption of 31-bit addressing.
- Feedback from prominent Model 67 users during development favored a 31-bit addressing limit over using all 32 bits.
Certain instructions operating in 31-bit mode adjust the addressing mode bit accordingly. Earlier subroutine call instructions such as (Branch and Link) and (Branch and Link Register) embedded status details—including instruction length code, condition code, and program mask—into the top byte of the return address. To accommodate return addresses within a 31-bit space, new instructions like (Branch and Save) and its register-to-register counterpart were introduced; these originated from the instruction set of the 360/67 and were adapted for use with 31-bit addressing.
Additional instructions facilitate transitions between code segments running in different addressing modes: (Branch and Save and Set Mode) stores both linkage address and current mode before branching to code potentially operating under a different mode, while (Branch and Set Mode) performs an unconditional return to a previously saved linkage address and mode. These mechanisms allow smooth switching between 24-bit and 31-bit modes during procedure calls and returns.
Examples include , which saves linkage information in register 14 before branching to an address and mode specified in register 15, and , which returns directly to the caller’s saved address and mode held in register 14 without preserving the current mode. These instructions maintain backward compatibility while extending addressing capabilities.
31-bit physical addressing
Originally, System/370 supported physical addresses limited to 24 bits; this was later expanded to 26 bits through the extended real address feature.
With System/370-XA, page table entries were redesigned to hold a 19-bit page frame address. Using a page size of 4 KB, combining this 19-bit page frame number with a 12-bit offset produces a physical address space of up to 31 bits. Channel command words accommodate two distinct formats: format 0 utilizes a standard System/370-style 24-bit data address, whereas format 1 supports a full 31-bit data address.
I/O
The System/370-XA implemented a channel subsystem designed to transfer I/O queuing responsibilities away from the operating system, thereby enhancing overall operational efficiency.