IBM System z10

IBM System z10
Company type	Product line
Industry	Mainframe computers
Founded	February 26, 2008; 18 years ago
Headquarters	Armonk, United States
Products	Mainframe computer systems (System z10 Enterprise Class, System z10 Business Class)
Parent	IBM

IBM System z10 represents a series of IBM mainframe systems. The z10 Enterprise Class (EC) was unveiled on February 26, 2008, followed by the introduction of the z10 Business Class (BC), a more compact variant, on October 21, 2008. This System z10 generation is the first to be driven by the z10 quad-core processor. Subsequent models include the zEnterprise System family released in 2010 and 2012.

Processors

The model number reflects the count of configurable processing units (PUs); for example, an E26 model contains 26 assignable PUs. Depending on the configuration, each PU can serve as a Central Processor (CP), Integrated Facility for Linux (IFL), z Application Assist Processor (zAAP), z10 Integrated Information Processor (zIIP), or Internal Coupling Facility (ICF) processor. Although specialty processors share identical hardware, their functionality is restricted by configuration. Additional System Assist Processors (SAPs) may be set up; however, most clients utilize only the minimum SAP allocation required for I/O and system support.

The total physical PUs surpass the number of configurable ones; for instance, the E12 model contains 17 physical PUs but only 12 are assignable—the remainder serve as spares or SAPs.

Operating systems

The System z10 is compatible with IBM operating systems such as z/OS, z/VSE, z/VM, and z/TPF. Alternative platforms include Linux on System z, OpenSolaris for System z, UTS, and MUSIC/SP. In 2008, Mantissa Corporation announced z/VOS to enable running x86-based operating systems like Windows and Linux on System z hardware; later renamed z86VM, its Linux support remains in beta with no plans for 64-bit capability, and Windows functionality is not yet available.

New features

Alongside enhanced performance, the System z10 introduced several significant mainframe innovations:

Cryptography

This system added hardware-accelerated support for 192-bit and 256-bit Advanced Encryption Standard (AES), extending beyond the 128-bit AES offered by the System z9.

Decimal floating point

While the System z9 utilized microcode-assisted IEEE 754 decimal floating point instructions, the System z10 integrates these operations natively within each processor core and instruction set architecture. This advancement boosts performance for Enterprise PL/I, XL C, and the z/OS Java BigDecimal class.

New instructions

The System z10 incorporates a range of new instructions designed to improve compiled code efficiency and execution speed. These instructions are utilized by the z/OS Java SDK. IBM’s z/VM Version 6.1 mandates these instructions to support virtualization expansion on System z10 and future platforms.

z/VM LPAR support

With System z10 and compatible versions of z/VM, a single logical partition (LPAR) can include all processor varieties, removing the prior requirement for separate LPARs to handle Linux processors (IFLs). This enhancement simplifies system management and configuration. Additionally, the z10 supports accelerated z/VM startup from DVD-RAM media. IBM provides a complimentary downloadable z/VM Evaluation Edition to promote user adoption.

Capacity on Demand improvements

The System z10 introduces a streamlined and automated framework for enabling and disabling Capacity on Demand (CoD) processing without the need for immediate IBM intervention. The newly introduced Capacity for Planned Events (CPE) feature permits temporary CPU activation at a reduced cost, designed specifically for activities such as data center relocations, system upgrades, and routine operational tasks.

InfiniBand coupling

System z10 incorporates support for InfiniBand coupling options within the IBM Parallel Sysplex environment, with certain configurations being retrofittable to the System z9. This enhancement boosts the high-speed interconnection capabilities between systems.

HiperDispatch

With the increase in core counts on System z servers, IBM tackled the challenges related to SMP performance limitations caused by cache, memory, and I/O resource contention. HiperDispatch is an advanced dispatching mechanism that coordinates between System z10 hardware and the z/OS operating system—particularly involving the Workload Manager and dispatcher—to allocate workloads to processor cores nearest to the required cached data. This approach minimizes contention for memory and I/O resources, supporting nearly linear scalability in SMP environments. Enabled by default across all System z10 models, HiperDispatch provides significant performance benefits, especially on larger-scale systems.

Models

IBM System z10 product family
	2007	2008	2009	2010	2011
Mainframe systems
Dual-rack	z9 EC	z10 E12		zEnterprise EC
		z10 E26
		z10 E40
		z10 E56
		z10 E64
Single-rack	z9 BC	z10 E10			zEnterprise BC

Enterprise Class

Released on February 26, 2008, the System z10 Enterprise Class lineup consists of five hardware variants: E12, E26, E40, E56, and E64 (machine type 2097). Each model is equipped with four-core PU chips operating at a clock speed of 4.4 GHz. The processors are installed in one to four "books," each housing multiple-chip modules containing processing units (PUs) alongside memory cards featuring multi-level cache architecture. The quantity of PUs per book differs depending on the specific model:

Model	Books / PUs	CPs	IFLs / uIFLs	zAAPs / zIIPs	ICFs	Opt SAPs	Std SAPs	Std Spares	Standard memory (GB)	Flexible memory (GB)
E12	1 / 17	0-12	0-12 / 0-11	0-6 / 0-6	0-12	0-3	3	2	16 - 352	NA
E26	2 / 34	0-26	0-26 / 0-25	0-13 / 0-13	0-16	0-7	6	2	16 - 752	32 - 352
E40	3 / 51	0-40	0-40 / 0-39	0-20 / 0-20	0-16	0-11	9	2	16 - 1136	32 - 752
E56	4 / 68	0-56	0-56 / 0-55	0-28 / 0-28	0-16	0-18	10	2	16 - 1520	32 -1132
E64	4 /77	0-64	0-64 /0-63	0-32 /0-32	0-16	0-21	11	2	16 -1520	32 -1136

NOTES:

Each model requires ordering at least one CP, IFL, or ICF.
For every CP ordered, one zAAP and one zIIP can be included.
Optional SAPs primarily apply to TPF/ESA or z/TPF implementations.
Memory specifications represent user-accessible capacity; the System z10 EC reserves a fixed portion of memory (16 GB) for Hardware System Area (HSA).
Configurations supporting sub-capacity CPs are available.

Business Class

Introduced on October 21, 2008, the z10 Business Class is available in a single variant: the E10 (machine type 2098). It utilizes the same processor chip architecture and instruction set as the z10 EC but achieves improved manufacturing yields by operating at a 3.5 GHz clock speed with one core per chip disabled. This results in cost-effective packaging due to diminished cooling requirements and reduced multi-chip cache complexity. The z10 BC also brought advancements in I/O packaging efficiency. It supports configurations without spare cores; under such setups, if a core fails, workloads are seamlessly transferred to the remaining cores automatically, ensuring uninterrupted application performance with a minor reduction in overall capacity.

Configuration options include:

Model	CPs	IFLs	zAAPs / zIIPs	ICFs	Standard memory (GB)
E10	1-5	1-10	0-5 / 0-5	1-10	4 - 120 (-248 as of June 2009)