IBM z13
| Company type | Microprocessor |
|---|---|
| Industry | Computer hardware |
| Founded | January 14, 2015 |
| Headquarters | East Fishkill, New York , United States |
| Products | z13 microprocessor |
The z13 microprocessor was created by IBM specifically for their z13 mainframe computer series, with its announcement occurring on January 14, 2015. Produced at the East Fishkill, New York facility of GlobalFoundries (previously owned by IBM), IBM positioned it as the fastest microprocessor worldwide at the time of release. It delivers roughly a 10% improvement in single-thread performance compared to its predecessor, the zEC12, along with substantially enhanced speeds for certain specialized tasks.
The IBM z13 represents the final z Systems machine to support operating systems running in ESA/390 architecture mode. Nevertheless, all existing 24-bit and 31-bit legacy applications continue to operate without modification.
Description
The Processor Unit (PU) chip spans 678 mm2 and incorporates 3.99 billion transistors. It is manufactured utilizing IBM's 22 nm CMOS silicon-on-insulator technology featuring 17 metal layers, capable of reaching clock rates up to 5.0 GHz—slightly below that of the zEC12. PU chips can be configured with six to eight cores each. Unlike earlier mainframe processors that employed multi-chip modules, the PU chip is delivered as a single-chip module. A single computer drawer accommodates six PU chips alongside two Storage Controller chips.
Each core executes the CISC z/Architecture instruction set through a superscalar, out-of-order execution pipeline. Notable enhancements include two-way simultaneous multithreading (SMT), 139 newly introduced SIMD instructions, improved data compression techniques, strengthened cryptographic functions, transactional memory support, and sophisticated logical partitioning features. The cores also benefit from a redesigned superscalar pipeline and extensive on-chip caches equipped with error correction.
The instruction pipeline can fetch up to six instructions per cycle and issue as many as ten. Dedicated private caches for each core consist of 96 KB L1 instruction cache, 128 KB L1 data cache, 2 MB L2 instruction cache, and 2 MB L2 data cache. Furthermore, a shared 64 MB L3 cache built with eDRAM technology is incorporated.
Memory controllers supporting multi-channel DDR3 are integrated into the z13, providing RAID-like fault tolerance. The processor also includes two GX buses and dual Gen 3 PCIe controllers to facilitate rapid connections to host channel adapters and peripheral devices.
Vector Facility
The z13 introduces a novel vector facility architecture featuring 32 vector registers that are each 128 bits wide; these overlay the existing set of 16 floating-point registers. This design enables support for over 150 new instructions targeting integer, floating-point, and string processing operations. To efficiently handle vector data workloads, the processor includes two separate SIMD execution units.
Storage Controller
Within each compute drawer are two clusters composed of three PU chips plus one Storage Controller (SC) chip each. While each PU chip contains a shared 64 MB L3 cache accessible by its eight cores, the SC chip adds an off-die L4 cache of 480 MB shared among the three PU chips in its cluster. Combined, the pair of SC chips in a drawer provides a total of 960 MB L4 cache and orchestrates communication between PU clusters as well as other drawers. Fabricated using a 22 nm process, the SC chip contains 7.1 billion transistors over an area of 678 mm² and runs at half the clock frequency of the CP chip.