IBM z14
| Company type | Microprocessor |
|---|---|
| Industry | Computer hardware |
| Founded | July 17, 2017 |
| Headquarters | East Fishkill , United States |
| Products | Microprocessor |
| Website | www |
The z14 is a microprocessor designed by IBM specifically for their z14 mainframe computer series, which was publicly introduced on July 17, 2017. Produced at the GlobalFoundries manufacturing facility located in East Fishkill, New York,[1] IBM promoted it as the fastest microprocessor globally by clock speed, reaching up to 5.2 GHz.[2] This chip delivers a 10% improvement in performance per core and an overall 30% increase compared to its predecessor, the z13.[3]
Description
The Processor Unit (PU) chip measures 696 mm2 and contains approximately 6.1 billion transistors,[4] manufactured using GlobalFoundries' advanced 14 nm FinFET silicon on insulator technology with a total of 17 metal interconnect layers. It supports clock frequencies up to 5.2 GHz, surpassing the capabilities of the z13.[4] The PU chip is equipped with 10 cores, which can be configured to enable between seven and ten active cores ("processor units"), each supporting two-way simultaneous multithreading to improve processing throughput.
This PU chip employs a single-chip module packaging approach, maintaining continuity from the previous generation but moving away from the earlier multi-chip module (MCM) designs. A system drawer incorporates six PU chips alongside one Storage Controller (SC) chip that contains the L4 cache.[4]
Each core operates using the CISC z/Architecture, featuring a superscalar, out-of-order execution pipeline. A significant addition in the z14 is the inclusion of a cryptographic coprocessor (CPACF) integrated into each core, which accelerates functions such as random number generation, hashing, encryption and decryption operations, as well as compression. Additional enhancements include pipeline refinements, doubling of on-chip cache sizes, improved branch prediction mechanisms, a decimal arithmetic SIMD engine optimized for languages like COBOL and PL/I, and a "guarded storage facility" designed to boost Java garbage collection efficiency.[4]
Each core possesses dedicated private caches: 128 KB L1 caches for both instructions and data, a 2 MB L2 instruction cache, and a separate 4 MB L2 data cache. Furthermore, a shared 128 MB L3 cache is implemented using eDRAM.[4]
The z14 integrates multi-channel DDR4 RAM memory controllers equipped with RAID-like fault tolerance features. It also includes two GX buses and dual Gen 3 PCIe controllers to support host channel adapters and peripheral devices.[4] Communication between the PU chips and the SC chip is facilitated through three X-buses on each PU chip.
Storage Controller
Within a compute drawer, there are two clusters, each comprising two or three PU chips, which collectively utilize a single Storage Controller chip (SC chip). Every PU chip includes 128 MB of L3 cache accessible to 10 cores, whereas the SC chip offers a substantial 672 MB off-die eDRAM L4 cache shared across all six PU chips in the drawer. The SC chip is responsible for coordinating data transfer both internally within the drawer and externally between drawers via the A-Bus. Produced using the same 14 nm manufacturing technology as the z14 PU chips, this chip incorporates 17 metal layers, spans an area of 25.3 × 27.5 mm (696 mm2), contains 9.7 billion transistors primarily due to its extensive L4 cache, and runs at half the clock speed of the PU chips.
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