IBM z15
| Company type | Microprocessor |
|---|---|
| Industry | Computer hardware |
| Founded | September 12, 2019 |
| Products | Microprocessor for IBM z15 mainframe computers |
The z15 represents a microprocessor engineered by IBM specifically for their z15 series of mainframe computers, which was officially revealed on September 12, 2019.
Description
This processor unit chip (PU chip) incorporates 12 cores, each capable of supporting dual-threaded simultaneous multithreading.
The cores utilize the CISC z/Architecture design, featuring a superscalar and out-of-order pipeline. Additionally, all cores share a novel on-chip nested accelerator unit that boosts compression efficiency.
Compared to its predecessor, the z14, the cache size has been substantially expanded: the level 3 cache capacity has doubled, while the level 4 cache has grown from 672MB to 960MB, marking a 43% increase through the use of an auxiliary chip known as the system controller (SC) SCM. Notably, every cache tier, including L1, employs eDRAM technology rather than conventional SRAM. In configurations with five CPC drawers, the total shared L4 cache amounts to 4800 MB (5 times 960 MB).