IBM z196
| Company type | Microprocessor |
|---|---|
| Industry | Semiconductor |
| Founded | July 22, 2010 |
| Headquarters | Poughkeepsie, New York; Austin, Texas; Böblingen, Germany , United States; Germany |
| Products | z196 microprocessor |
| Parent | IBM |
The z196 microprocessor is a semiconductor chip created by IBM specifically for their zEnterprise 196 and zEnterprise 114 mainframe systems, officially introduced on July 22, 2010. The development spanned three years and involved teams located in Poughkeepsie, New York, Austin, Texas, and Böblingen, Germany, with a total investment of US$1.5 billion. Production commenced on September 10, 2010, at IBM's manufacturing facility in Fishkill, New York. At the time of its release, IBM asserted it was the fastest microprocessor worldwide.
Description
The chip measures 512.3 mm2 and houses 1.4 billion transistors built using IBM’s 45 nm CMOS silicon-on-insulator technology. It supports clock frequencies reaching up to 5.2 GHz, which represented the highest commercially available speed during its launch.
This processor executes the CISC z/Architecture instruction set architecture with a novel superscalar, out-of-order execution pipeline and introduces 100 additional instructions. Its pipeline consists of 15 to 17 stages and includes an instruction queue capable of holding as many as 40 instructions, with up to 72 instructions processed simultaneously. The quad-core configuration features private caches per core: 64 KB L1 instruction cache, 128 KB L1 data cache, and a 1.5 MB L2 cache, complemented by a shared 24 MB L3 cache implemented in eDRAM under the control of two on-chip cache controllers. There is also a dedicated shared L1 cache designed to accelerate compression and cryptography workloads.
Each core incorporates six execution units resembling RISC architecture: two integer units, two load/store units, one binary floating-point unit, and one decimal floating-point unit. The z196 can decode three instructions per cycle and execute five operations concurrently within each clock cycle.
Integrated on the chip is a DDR3 memory controller featuring RAID-like error correction capabilities along with a GX bus controller that manages host channel adapters and peripheral interfaces. Additionally, specialized co-processors are embedded for cryptographic processing and data compression functions.
The z196 processor supports on-chip symmetric multiprocessing (SMP) functionality and is complemented by two dedicated Shared Cache (SC) companion chips. Each SC chip provides 96 MB of off-die L4 cache memory, resulting in a combined total of 192 MB shared among all processors in the system. These SC chips contain approximately 1.5 billion transistors each, occupy an area of 478.8 mm2, and are manufactured using the same 45 nm fabrication process as the z196 processor itself.
Furthermore, each individual processor contains an integrated 24 MB L3 cache that is shared across its four cores.
Multi-chip module
Within the IBM zEnterprise System z196 platform, multi-chip modules (MCMs) are employed that package six z196 processors together on a single module. Each MCM also includes two shared cache chips which facilitate inter-processor communication at bandwidths reaching 40 GB/s.
To create product differentiation among various models, some processors within an MCM may have their fourth core disabled. This approach allows IBM to offer different performance levels and capacities tailored to customer requirements.
z114
The zEnterprise System z114 utilizes z196 processors configured as single chip modules (SCMs) rather than multi-chip modules. Each drawer in this system contains two SCMs along with one Shared Cache chip. These processors operate at a lower clock speed of 3.8 GHz to serve distinct market segments with adjusted performance characteristics and pricing structures.