Josh Fisher

Joseph A. Fisher
Born	Joseph A Fisher (1946-07-22) July 22, 1946 The Bronx, New York, USA
Other names	Josh Fisher
Occupation	Computer scientist
Years active	1979–2006
Known for	Contributions to VLIW architectures, compiler design, instruction-level parallelism; co-founder of Multiflow Computer; Senior Fellow at Hewlett-Packard
Notable work	Trace Scheduling algorithm; co-author of Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools

Joseph A "Josh" Fisher (born July 22, 1946) is a dual American and Spanish computer scientist renowned for his groundbreaking contributions to VLIW architectures, compiler design, and instruction-level parallelism. He also co-founded Multiflow Computer and served as a Senior Fellow at Hewlett-Packard before retiring.

Biography

Fisher completed his undergraduate studies with honors in mathematics at New York University in 1968, earning a BA. He then pursued graduate education at NYU's Courant Institute, obtaining both a Master's and a PhD in Computer Science by 1979.

Beginning his academic career at Yale University’s Computer Science Department in 1979 as an assistant professor, Fisher was promoted to associate professor by 1983. The following year, he departed Yale to establish Multiflow Computer alongside John O'Donnell and John Ruttenberg. After Multiflow ceased operations in 1990, Fisher joined HP Labs, where he led the Cambridge, Massachusetts research center from its founding in 1994. His achievements earned him the titles of HP Fellow in 2000 and Senior Fellow in 2002, prior to his retirement in 2006.

Fisher has been married to Elizabeth Fisher since 1967 and they have two children. He also holds Spanish nationality, which he obtained through his Sephardic ancestry.

Trace Scheduling

During his doctoral research, Fisher introduced the Trace Scheduling algorithm for compilers and originated the term Instruction-level parallelism to characterize architectures such as VLIW, superscalar, and dataflow that exploit fine-grained parallel execution of machine instructions. Trace scheduling was pioneering as the first effective approach to leverage parallelism beyond single basic blocks, greatly enhancing performance potential in instruction-level parallel systems.

The VLIW architecture style

To overcome limitations applying trace scheduling on specialized hardware like the digital signal processors of the 1970s, Fisher proposed the VLIW architectural paradigm. VLIW machines are conventional computers that execute compiled programs but achieve substantial instruction-level parallelism through compiler-driven scheduling techniques like trace scheduling. Today, VLIW designs are prevalent especially within embedded systems; some widely adopted VLIW cores have reached billions of units sold. For instance, Qualcomm’s Hexagon 4-issue VLIW cores have been part of Snapdragon processors since 2006, and the ST231 core has reportedly exceeded one billion units shipped primarily for digital video processing.

Multiflow Computer

The creation of Multiflow aimed to bring trace scheduling and VLIW concepts—then viewed as impractical—to commercial viability. The company’s technological breakthroughs and diffusion of its innovations and personnel had a lasting impact on both computer science research and industry practices.

Awards and honors

• 1984 NSF Presidential Young Investigator Award (declined funding after leaving Yale for Multiflow)
• 1987 Eli Whitney Connecticut Entrepreneur of the Year
• 2003 Eckert–Mauchly Award from IEEE Computer Society and ACM recognizing over two decades of foundational work in instruction-level parallelism, pioneering contributions to VLIW architectures, and development of the Trace Scheduling compilation method—regarded as the premier accolade in computer architecture
• 2012 B. Ramakrishna Rau Award from IEEE Computer Society honoring his role in creating trace scheduling compilation techniques and advancing VLIW architecture design

Writings

• Joseph A. Fisher, Paolo Farabochi, and Cliff Young authored Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools, published by Elsevier/Morgan Kaufmann in 2004.
• Joseph A. Fisher presented Trace Scheduling: A Technique for Global Microcode Compaction, featured in IEEE Transactions on Computers, volume 30, issue 7, pages 478–490, in 1981.
• Joseph A. Fisher discussed Very Long Instruction Word Architectures and the ELI-512 in the proceedings of ISCA '83, the 10th annual international symposium on Computer Architecture, pages 140–150, published by ACM in New York, NY, USA. This work was revisited in the retrospective 25 Years of ISCA, ACM, 1998.
• In collaboration with John R. Ellis, John C. Ruttenberg, and Alexandru Nicolau, Joseph A. Fisher wrote Parallel Processing: A Smart Compiler and a Dumb Machine, presented at the Symposium on Compiler Construction in 1984 (pages 37–47). This paper was later included in the retrospective collection Best of PLDI, ACM SIGPLAN Notices, volume 39, issue 4, page 112, in 2003.
• B. Ramakrishna Rau and Joseph A. Fisher co-authored Instruction-level parallel processing: history, overview, and perspective, published in The Journal of Supercomputing's special issue on instruction-level parallelism, volume 7, issues 1–2, May 1993. This article was also released by Kluwer Academic Publishers.

External links

• Elizabeth Fisher's book titled Multiflow Computer: A Startup Odyssey is available through CreateSpace, published in 2013.
• IEEE published two parts titled The VLIW Architecture of Joseph A. Fisher in Solid-State Circuits Magazine, volume 1, issue 2, in 2009; both Part 1 and Part 2 can be accessed via IEEE Xplore.