Kendall Square Research
| Company type | Private |
|---|---|
| Industry | Supercomputing |
| Founded | 1986 |
| Founder | Steven Frank, Henry Burkhardt III |
| Defunct | 1994 |
| Fate | Bankruptcy |
| Headquarters | Cambridge, Massachusetts , United States |
| Products | KSR1, KSR2 supercomputers |
Kendall Square Research (KSR) was a supercomputing firm established in 1986, located in Kendall Square, Cambridge, Massachusetts, close to MIT. The company was co-founded by Steven Frank and Henry Burkhardt III, the latter being a seasoned entrepreneur with prior involvement at Data General and Encore Computer. KSR designed and released the KSR1 and KSR2 supercomputers before ultimately declaring bankruptcy in 1994.
Technology
The KSR machines ran on a tailored variant of the OSF/1 Unix operating system, utilizing compilers for C and FORTRAN developed specifically by Green Hills for KSR hardware. Their architecture was based on a shared memory model implemented through a cache-only memory architecture (COMA), which allowed for adaptive memory migration and replication depending on processor access patterns. Processors were arranged in hierarchical ring structures, with the operating system overseeing process migration and device management. Each processor in the KSR1 was a custom-built 64-bit RISC CPU clocked at 20 MHz, capable of delivering 20 MIPS and 40 MFLOPS; these systems could scale up to 1088 processors. The successor, KSR2, doubled the clock frequency to 40 MHz and expanded scalability beyond 5000 processors. Sharp Corporation manufactured the chipsets for the KSR-1, while Hewlett-Packard handled those for the KSR-2.
Software
KSR targeted both scientific research and commercial sectors, including large-scale parallel database applications, forming a partnership with Oracle Corporation. Their platforms supported Micro Focus COBOL, C/C++, Oracle Database, and ADB Inc.'s MATISSE object-oriented database management system. An exclusive component called KSR Query Decomposer enhanced Oracle's SQL functionality. Furthermore, the TUXEDO transaction monitor enabled support for online transaction processing (OLTP) workloads. Development was aided by tools such as the KAP preprocessor for code analysis and automatic parallelization, alongside the PRESTO runtime environment that managed POSIX-compliant multithreading.
Hardware
The processor in the KSR-1 was composed of four integrated chips fabricated using 1.2-micron CMOS technology: the cell execution unit (CEU), floating point unit (FPU), arithmetic logic unit (ALU), and external I/O unit (XIO). The CEU handled fetching two instructions per clock cycle as well as memory operations, initially supporting 40-bit addressing with plans to extend to full 64-bit addresses. The integer execution unit contained thirty-two registers of 64 bits each. The XIO facilitated I/O device communication at speeds up to 30 MB/s and incorporated 64 control and data registers.
KSR's processor architecture employed a two-wide very long instruction word (VLIW) design featuring six categories of instructions: memory reference, execute, control flow, memory control, I/O, and inserted instructions. Execute instructions encompassed arithmetic operations, logical functions, and type conversions generally formatted as three-register operations. Control flow instructions included branches and jumps with two-cycle latency; programmers or compilers could specify whether subsequent instructions were nullified during branching. Memory control instructions provided synchronization mechanisms; I/O instructions managed device interactions. Inserted instructions were controlled by coprocessors to handle DMA transfers and maintain cache coherence. The system complied with IEEE 754 floating point standards using sixty-four registers of 64 bits each.
Programming at the assembly level demanded explicit scheduling due to the absence of interlocks combined with two-cycle delay slots, which could introduce hazards if not properly handled.
The KSR design treated all memory uniformly as cache without assigning fixed "home" locations, allowing dynamic migration and replication transparently based on access patterns to optimize storage efficiency. It utilized a Harvard architecture featuring separate buses for instructions and data. Each node board contained 256 KB of primary instruction and data cache plus 32 MB of main cache memory. The shared virtual memory model presented a unified contiguous address space spanning 40 bits distributed physically across nodes; inter-node communication bandwidth reached up to 4 GB/s. The collective node memories constituted the machine's total physical memory.
Scalable input/output capabilities were provided through dedicated I/O processors; a fully configured KSR1 system with 1088 nodes could support as many as 510 I/O channels delivering combined throughput exceeding 15 GB/s. Supported network interfaces included Ethernet, FDDI, and HIPPI.
History
During the late 1980s, as KSR increased its production capacity, it moved its operations to 170 Tracer Lane in Waltham, Massachusetts. The company transitioned its focus from primarily scientific applications to targeting commercial markets, placing greater emphasis on parallel relational database systems and online transaction processing (OLTP). While KSR discontinued manufacturing hardware, it maintained its involvement in marketing software solutions for data warehousing and analytical purposes.
The initial KSR1 system was introduced in 1991, showcasing innovative processor and memory components alongside a unique memory architecture and a ported operating system. Early versions of the KSR1 were prone to frequent system failures, earning the system the nickname Allcrash, although these issues were not always related to memory faults. Sales of the KSR1 remained limited before the launch of the KSR2; however, the company ultimately collapsed amid financial discrepancies involving inflated revenue reports.
Due to a lack of suitable commercial processors, KSR engineered its own proprietary 64-bit processors, integrating both processor and system design—a complex business strategy. The 1991 KSR processors operated at 20 MHz with a performance of 40 MFlops, which was behind the Intel 80486’s 50 MHz and 50 MFlops capabilities. The subsequent 1992 KSR2 model doubled the clock speed to 40 MHz and achieved 80 MFlops but still fell short compared to the DEC Alpha’s 192 MHz and 192 MFlops performance.
A noteworthy example is the Pacific Northwest National Laboratory, part of the United States Department of Energy, which invested significantly in spare components to keep their KSR2 machines operational following the company’s bankruptcy. Like many supercomputer firms in the early 1990s, KSR succumbed to the market downturn and ceased operations in February 1994 after being removed from the stock exchange.
In April 1996, the SEC brought charges against several KSR executives—including CEO Henry Burkhardt III, sales executive Peter Appleton Jones, CFO Karl Wassman III, and contracts director Thomas J MacCormack—for issuing misleading financial reports during 1992–1993 and engaging in insider trading. Although none admitted guilt, all parties resolved the allegations by paying disgorgements, penalties, and interest. Burkhardt’s payment totaled about $1.1 million; other executives paid smaller sums, with some penalties waived due to financial hardship.
Competition
KSR faced competition from companies such as MasPar Computer Corporation, Thinking Machines, Meiko Scientific, as well as major industry players like IBM and Intel.