Program status word

IBM System/360

Industry	Computer hardware
Founded	1964 (1964)
Headquarters	Armonk , United States
Products	Mainframe computers, including System/360 series
Website	www.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP360.html

The program status word (PSW) serves as a register that combines the roles of a status register and a program counter, predominantly within the IBM System/360 and its subsequent models. IBM designates bit numbering starting from 0 as the highest-order bit.

Certain fields within the PSW are accessible by instructions without special privileges, whereas others demand privileged instruction access.

Embedded in the PSW is a two-bit condition code that signals statuses such as zero, positive, negative, and overflow. Conditional branch operations evaluate this as a four-bit entity, with each bit representing one of these condition codes.

The 64-bit PSW encompasses critical components including:

• Interrupt mask settings
• Privilege level indicators
• Condition code
• Instruction address

In earlier designs like System/360 and initial System/370 versions, the instruction address was 24 bits in length; this was extended to 31 bits plus an additional mode bit (totaling 32 bits) in XA/370. Modern z/Architecture systems utilize a 64-bit instruction address embedded within a 128-bit PSW.

The PSW is updated through the LOAD PSW instruction (LPSW or LPSWE) and can be retrieved using the Extract PSW instruction (EPSW).

S/360

Apart from the 360/20, the S/360 PSW adheres to these specified formats. The Extended PSW format is applicable solely to the 360/67 when bit 8 of control register 6 is activated.

IBM S/360 PSW formats

S/360 Standard PSW System Mask Key A M W P Interruption Code ILC CC Program Mask Instruction Address

|} |} |}

S/370

IBM S/370 PSW formats

S/370 Basic Control mode PSW Chan. Mask I O E X Key 0 M W P Interruption Code 0 1 2 4 5 6 7 8 11 12 13 14 15 16 ILC CC Program Mask Instruction Address

|} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |} |}

S/370 Extended Control mode PSW format
Bit	R	T	IO	EX	Key (4 bits)	M	W	P	S	CC (2 bits)	PM (4 bits)	Instruction Address (24 bits)
Values	Various control bits including: R – PER Mask T – DAT mode IO – I/O Mask subject to channel mask in CR2 EX – External Mask subject to external subclass mask in CR0 Key – PSW key for storage protection M – Machine-check mask W – Wait state P – Problem state S – Address-Space Control (primary or secondary space) CC – Condition Code PM – Program Mask flags (overflow, underflow, significance) Instruction Address – Next instruction location
Notes	Extended Control mode indicated by E=1 bit.

1 || R || PER Mask (Program Event Recording) 5 || T || DAT mode (Dynamic Address Translation) 6 || IO || I/O Mask, subject to channel mask in CR2 register 7 || EX || External Mask, subject to external subclass mask in CR0 register 8-11 || Key || PSW key for storage protection and access control 12 || E=1 || Extended Control mode indicator bit set to one 13 || M || Machine-check mask to enable or disable machine checks 14 || W || Wait state flag controlling processor wait conditions 15 || P || Problem state flag indicating user or supervisor mode 16 || S || Address-Space Control bit (0 = primary space, 1 = secondary space) 18-19 || CC || Condition Code reflecting operation results 20-23 || PM || Program Mask flags including fixed-point overflow, decimal overflow, exponent underflow, and significance:

Bits	Field	Meaning

20 || Fixed-point overflow 21 || Decimal overflow 22 || Exponent underflow 23 || Significance flag

Bit	Meaning

40-63 || IA || Instruction Address specifying next instruction location to execute.

S/370 Extended Architecture (S/370-XA)

IBM Extended Architecture (XA) PSW layout

Extended Architecture Extended Control mode PSW 0 R 0 0 0 T I O E X Key 1 M W P S 0 CC Program Mask 0 0 0 0 0 0 0 0 A Instruction Address

|}

Enterprise Systems Architecture (ESA)

IBM Enterprise Systems Architecture (ESA) PSW layout

Enterprise Systems Architecture Extended Control mode PSW format 0 R 0 0 0 T I O E X Key 1 M W P AS CC Program Mask 0 0 0 0 0 0 0 0 style="width:1%; text-align:left; border-style:none;">0 style="width:1%; text-align:left; border-style:none;">1 style="width:1%; text-align:left; border-style:none;">2 style="width:1%; text-align:right; border-style:none;">4 style="width:1%; text-align:left; border-style:none;">5 style="width:1%; text-align:left; border-style:none;">6 style="width:1%; text-align:left; border-style:none;">7 style="width:1%; text-align:left; border-style:none;">8

|}

1 || R || PER Mask 5 || T || DAT mode 6 || IO || I/O Mask, influenced by channel mask in CR2 7 || EX || External Mask, controlled by external subclass mask in CR0 8-11 || Key || PSW key 12 || E=1 || Extended Control mode activated 13 || M || Machine-check mask 14 || W || Wait state indicator 15 || P || Problem state flag 16-17 || AS || Address-Space Control modes:
00=primary, 01=Access-register, 10=Secondary, 11=Home space 18-19 || CC || Condition Code 20-23 || PM || Program Mask bits:

Bits	Field	Description

20 || Fixed-point overflow 21 || Decimal overflow 22 || Exponent underflow (renamed HFP exponent underflow in ESA/390) 23 || Significance (renamed HFP significance in ESA/390)

Bit	Description

z/Architecture

IBM z/Architecture PSW structures

z/Architecture long PSW

|}

1 || R || PER Mask 5 || T || DAT mode 6 || IO || I/O mask 7 || EX || External Mask 8-11 || Key || PSW key 12 || E=0 || Must be zero for LPSWE instruction 13 || M || Machine-check mask 14 || W || Wait state indicator 15 || P || Problem state flag 16-17 || AS || Address-Space Control (00=primary-space,01=Access-register,10=Secondary-space,11=Home-space) 18-19 || CC|| Condition Code 20-23|| PM ||

Bits	Field	Explanation

20|| Fixed-point overflow 21|| Decimal overflow 22|| HFP Exponent underflow 23|| HFP Significance

Bit	Explanation

24|| RI|| Reserved for IBM use

31|| EA|| Extended Addressing mode (0=defined by BA;1=64-bit addressing with BA zero)

32|| BA|| Basic Addressing mode (0=24 or 64-bit;1=31-bit)

64-127|| IA|| Instruction Address field

z/Architecture short PSW (format details omitted)

1|| R|| PER Mask 5|| T|| DAT mode 6|| IO|| I/O mask 7|| EX|| External Mask 8-11|| Key|| PSW key 12|| E=1|| Must be one for LPSW instruction 13|| M|| Machine-check mask 14|| W|| Wait state indicator 15|| P|| Problem state flag 16-17|| AS|| Address-Space Control (00=primary-space,01=Access-register,10=Secondary-space,11=Home-space) 18-19|| CC|| Condition Code 20-23|| PM||

Bits	Field	Description

20|| Fixed-point overflow 21|| Decimal overflow 22|| HFP Exponent underflow 23|| HFP Significance

Bit	Description

24|| RI|| Reserved for IBM use

31|| EA|| Extended Addressing mode (0=set by BA;1=enables 64-bit with BA zero)

32|| BA|| Basic Addressing mode (0 selects 24 or 64-bit;1 selects 31-bit)

33-63|| IA|| Instruction Address

References

S360

func67

S370

S370-XA

S370-ESA

z