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QCDOC

From Alfawiki
QCDOC
Company typeCollaborative research project
IndustrySupercomputing, Quantum physics simulation
FounderUniversity of Edinburgh (UKQCD), Columbia University, RIKEN BNL Brookhaven Research Center, IBM
Headquarters
United Kingdom, United States, Japan
Area served
Worldwide research community
ProductsQCDOC supercomputer system
Number of employees
23 (UKQCD collaboration researchers)

The QCDOC (quantum chromodynamics on a chip) represents a supercomputing innovation that utilizes energy-efficient processing units to establish a highly parallel computing architecture. Its design specifically targets the resolution of intricate challenges in quantum physics.

Overview

The creation of QCDOC was a joint effort involving the University of Edinburgh (UKQCD), Columbia University, the RIKEN BNL Brookhaven Research Center, and IBM. This initiative focused on advancing computational power for calculations in lattice field theory, thereby enhancing numerical simulations of quantum chromodynamics (QCD) to refine predictions within the Standard Model. The objective was to develop a supercomputer capable of reaching a peak performance of 10 Tflops with sustained throughput at approximately 50%.

Currently, three QCDOC installations achieve peak speeds of 10 Tflops each:

  • The Parallel Computing Centre (EPCC) at the University of Edinburgh, operational since 2005
  • RIKEN BNL Brookhaven Research Center located at Brookhaven National Laboratory
  • The U.S. Department of Energy's High Energy and Nuclear Physics Program at Brookhaven National Laboratory

The UKQCD collaboration consists of roughly 23 researchers, including academic staff, postdoctoral fellows, and students from seven UK institutions. Financial support comprised a £6.6 million award from the Joint Infrastructure Fund, with annual personnel expenditures near £1 million and operational costs around £0.2 million.

QCDOC followed the earlier QCDSP system, which linked over 12,000 DSP units in a four-dimensional network to achieve 1 Tflops in 1998.

This system served as a foundation for the later successful Blue Gene/L supercomputer. Both architectures utilize numerous cost-effective, relatively simple PowerPC 440 based SoC processors interconnected through multidimensional mesh topologies. Nevertheless, Blue Gene/L incorporates more advanced nodes and a faster, more scalable network infrastructure capable of supporting several hundred thousand nodes per configuration.

Computing node

Each computing node is a custom-designed ASIC containing approximately fifty million transistors, primarily assembled from existing components supplied by IBM. The node integrates a 500 MHz PowerPC 440 processor core, 4 MB of embedded DRAM, memory management logic for external DDR SDRAM, system I/O facilitating inter-node communication, and dual Ethernet interfaces. Performance per node reaches 1 double precision Gflops, and each supports one DIMM slot accommodating between 128 and 2048 MB of 333 MHz ECC protected DDR SDRAM.

Inter node communication

Communication between nodes occurs with their twelve closest neighbors across a six-dimensional mesh network operating at 500 Mbit/s per connection, yielding an aggregate off-node bandwidth of 12 Gbit/s. Each of the 24 communication channels includes DMA capabilities to either on-chip DRAM or external SDRAM. Typically, four dimensions form a communications sub-torus while the remaining two dimensions are used to partition the overall system.

The operating system manages node interaction through Ethernet connections for purposes such as diagnostics, configuration, and interfacing with disk storage systems.

Mechanical design

Each pair of nodes is connected via a shared daughter card that includes a single DIMM slot and a 4:1 Ethernet hub facilitating off-card communication. These daughter cards are equipped with connectors dedicated to internode networking, power delivery, Ethernet connectivity, clock synchronization, and system management tasks.

A total of thirty-two daughter cards are installed in two rows on a motherboard, which supports off-board Ethernet at speeds up to 800 Mbit/s. Eight such motherboards are housed within crates, each crate containing two backplanes that accommodate four motherboards apiece. Within each crate, 512 processor nodes are arranged in a 26 hypercube topology. Individual nodes typically consume approximately 5 watts of power, while the crates employ both air and water cooling systems. The architecture allows for expansion to tens of thousands of nodes by integrating additional crates.

Operating system

The QCDOC system operates using QOS, a specialized operating system designed to handle boot procedures, runtime management, monitoring, diagnostics, and performance optimization across numerous nodes. It incorporates an embedded kernel that offers single-process POSIX compatibility through the Cygnus newlib library. This kernel also integrates a proprietary UDP/IP stack alongside an NFS client to facilitate disk operations.

QOS features support for system partitioning, enabling multiple users to execute distinct applications concurrently. Within each partition, only one client application runs at any given time; multitasking across partitions is coordinated by the host controller system—a conventional computer linked via an extensive array of Ethernet ports.

See also

References

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