Rajiv Joshi
Rajiv V. Joshi | |
|---|---|
| Born | India |
| Occupation(s) | Inventor, research scientist |
| Years active | 1977–present |
| Known for | Integrated circuit technology, memory chip development |
Rajiv V. Joshi is a distinguished Indian-American inventor and a research scientist at IBM's Thomas J. Watson Research Center. His expertise lies in the advancement of integrated circuit technology and memory chip development. An IEEE Fellow, Joshi was honored with the Industrial Pioneer Award by the IEEE Circuits and Systems Society in 2013 and later received the IEEE Daniel E. Noble Award in 2018. With a portfolio exceeding 300 U.S. patents, he was appointed Vice-President of Industry for the IEEE Circuits and Systems Society (CASS) in 2025.
Education
Joshi completed his bachelor of technology degree in mechanical engineering at the IIT Bombay. In 1977, he relocated to the United States to pursue graduate studies, obtaining a master's degree from the MIT followed by a Ph.D. from Columbia University.
Technical Innovations
Integrated Circuit Interconnect
Joshi spearheaded breakthroughs in materials used for integrated circuit interconnects, focusing on refractory metal contacts, liners, deposition processes, chemical mechanical polishing, and large grain copper applications. These innovations facilitated the transition from aluminum to copper wiring, enabling multi-layer interconnect architectures essential for chip miniaturization with reduced power consumption. Contemporary microprocessors now integrate over 15 billion transistors interconnected by more than 50 kilometers of copper wiring.
Predictive Failure Analytics for Big Data
He introduced methods that significantly accelerated Predictive Analytics, allowing failure rate estimations and objective optimizations to be performed five to six orders of magnitude faster than traditional approaches. This work has had a substantial impact on research within various CAD companies.
Advanced Integrated Circuit Memory
Joshi was a pioneer in developing high-speed memory solutions such as MRAM, TRAM, and In-Memory computation technologies. These innovations have pushed memory scalability beyond Moore's Law constraints while improving bandwidth, system performance, and data transfer efficiency.
Technology-Circuit Co-design
He demonstrated the inaugural high-performance register file that played a pivotal role in transitioning from bulk silicon to SOI technology. Additionally, Joshi contributed to introducing FinFET implementations for low-power yet high-performance SRAM designs and proposed strained non-planar device structures—FinFETs have since become widely adopted throughout the semiconductor industry.
Low Power Circuits
Joshi designed energy-efficient low-power circuit architectures critical for VLSI operation and emerging Internet of Everything (IoE) applications. His recent development of ultra-low voltage memory operating at 0.3V attracted notable coverage in EE Times.
Awards
- Awarded "Inventor of the Year" by the New York Intellectual Property Law Association in 2020.
- Joined the Board of Governors for IEEE Circuits and Systems Society in 2019.
- Honored with the 2018 IEEE Daniel E. Noble Award recognizing Emerging Technologies.
- Named Fellow of the World Technology Network in December 2016.
- Recognized as Best Editor for IEEE Transactions on VLSI Systems in July 2016.
- Inducted into the New Jersey Inventor Hall of Fame in 2014 alongside figures such as Nikola Tesla.
- Received the Industrial Pioneer Award from IEEE Circuits and Systems Society in 2013.
- Winner of the IEEE/ACM William J. McCalla ICCAD Best Paper Award in 2009.
- Honored with Distinguished Alumnus Award from Indian Institute of Technology Bombay in 2008.
- Designated Fellow at IEEE International Symposium on Quality Electronics and Design (ISQED) in 2007.
- Named IEEE Fellow since 2001 for significant contributions to chip metallurgy materials, fabrication processes, and high-performance processor and circuit design.