SDS 930
| Industry | Computer hardware |
|---|---|
| Headquarters | United States |
| Products | SDS 930 computer |
The SDS 930 was a commercially available 24-bit computer constructed with bipolar junction transistor technology and marketed by Scientific Data Systems. Its announcement occurred in December 1963, with initial deployments starting in June 1964.
Description
A typical SDS 930 setup consisted of a minimum of three standard () cabinets, collectively weighing approximately .[1] The system incorporated an arithmetic and logic unit, at least 8,192 words of 24-bit magnetic-core memory equipped with parity checking, and an input/output unit. It operated using two's complement format for integer calculations, supporting integer multiplication and division but did not include hardware for floating-point operations.[2] An optional correlation and filtering unit (CFE) provided accelerated floating-point multiply-add functionality geared towards digital signal processing tasks.
The standalone control console was outfitted with binary indicator lights and switches designed for system bootstrapping and debugging purposes. User interaction was primarily handled through a Teletype Model 35 ASR along with a high-speed paper-tape reader capable of processing 300 characters per second. Common peripheral configurations featured two magnetic tape drives (operating up to 75 inches per second at 800 bits per inch), as well as devices such as magnetic drums, card readers and punches, and analog-to-digital converters. A vector graphics display unit was offered but lacked keyboard input capabilities.
Engineered as a scientific computer suitable for small to medium-scale applications during the 1960s, the SDS 930 delivered competitive cost-efficiency; however, its integer addition time of 3.5 microseconds constrained performance relative to top-tier machines like the CDC 6600. Fully expanded installations could surpass ten cabinets and necessitated an environment with controlled temperature and humidity. By 1966, the price point neared $500,000.
Programming languages supported included FORTRAN II, ALGOL 60, and the assembly language Meta-Symbol. Digitek’s streamlined FORTRAN compiler leveraged the SDS architecture’s Programmed OPeratorS (POPS) feature—where a specific bit in the instruction word invoked software-defined pseudo instructions—enabling compact and efficient specialized coding within limited memory space.
Towards the latter part of its commercial lifespan, a real-time monitor system accompanied by a FORTRAN IV compiler was introduced but experienced limited market penetration. Numerous customers modified the SDS 930 hardware extensively; notably, UC Berkeley’s Project Genie enhanced it with time-sharing capabilities that eventually led to the development of the SDS 940. Additional user-created operating systems included Arachnid at the University of Texas at Austin.
The SDS 930 saw extensive use in prominent U.S. government laboratories such as Los Alamos Scientific Laboratory. Its built-in integer multiplication/division hardware combined with real-time peripheral modules made it well suited for early flight simulation environments as well as real-time data acquisition and control applications.
One notable use case was the Surface Ship ASW Attack Trainer (Device 14A2A), where an SDS 930 served to train U.S. Navy destroyer anti-submarine warfare teams through realistic shore-based simulations that helped reduce operational expenses at sea.
By the year 1974, roughly 200 units from the SDS-930/940/945 series remained operationally installed.