SDS Sigma series
| Company type | Public |
|---|---|
| Industry | Computer hardware |
| Founded | 1966 |
| Headquarters | United States |
| Products | SDS Sigma series computers |
The SDS Sigma series represents a range of third generation computers launched by Scientific Data Systems (SDS) in 1966. The initial offerings included the 16-bit Sigma 2 and the 32-bit Sigma 7, with the latter being SDS's inaugural 32-bit machine. At that period, its chief rival was the IBM System/360.
Sigma computers utilize byte-addressed memory, but their capacity is measured in kilowords rather than kilobytes. For example, the base memory of the Sigma 5 consisted of 16,384 32-bit words (equivalent to 64 kB), expandable up to 128 kilowords (512 kB), constrained by a 17-bit instruction address field. While these sizes may seem limited today, they were adequate for the majority of applications at the time.
The design of the Sigma series served as a foundation for later machines: the CII 10070 was essentially a rebranded Sigma 7 and provided the architecture for the compatible Iris 50 and Iris 80 systems. Additionally, beginning in 1973, the Xerox 500 series offered backward-compatible enhancements incorporating more advanced technology.
In 1975, Xerox divested its computer division to Honeywell, Inc., which maintained support for the Sigma product line for several years thereafter.
The Sigma 9 model is distinguished by its extended operational lifespan while retaining prices close to its original retail cost. It was still functional as late as 1993. In 2011, the Living Computer Museum in Seattle obtained a Sigma 9 from a service bureau and successfully restored it to working order. Prior to this, its CPU had been utilized at the University of Southern Mississippi, followed by Andrews University, before being sold to Applied Esoterics in Arizona. Restoration culminated in running the CP-V operating system by late 2014, with supplementary parts sourced from various users including Marquette University and Xerox/Dallas.
32-bit systems
| Model | Release Year | Floating Point Support | Decimal Support | Byte String Support | Memory Mapping | Maximum Memory (kwords) |
|---|---|---|---|---|---|---|
| Sigma 7 | 1966 | optional | optional | standard | optional | 128 |
| Sigma 5 | 1967 | optional | not applicable | not applicable | not applicable | 128 |
| Sigma 6 | 1970 | optional | standard | standard | standard | 128 |
| Sigma 9 | 1971 | standard | standard | standard | standard | 512 |
| Sigma 8 | 1972 | standard | not applicable | not applicable | not applicable | 128 |
| Sigma 9 model 2 | 1972 | standard | standard | standard | standard | 256 |
| Sigma 9 model 3 | 1973 | standard | not applicable | not applicable | standard | 512 |
16-bit systems
| Model | Release Year | Maximum Memory (kwords) |
|---|---|---|
| Sigma 2 | 1966 | 64 |
| Sigma 3 | 1969 | 64 |
Instruction format
Memory-reference instructions on the 32-bit Sigma models follow this layout:
+-+--------------+--------+------+---------------------------+ |*| Op Code | R | X | Reference address | +-+--------------+--------+------+---------------------------+ bit0 bits1-7 bits8-11 bits12-14 bits16-31 Bit 0 signals an indirect address. Bits 1-7 contain the operation code (opcode). Bits 8-11 specify a register operand (values from 0 to15). Bits12-14 designate an index register (1–7); zero indicates no indexing. Bits16-31 hold the memory word address.
For the Sigma 9 equipped with extended addressing capability, interpretation of the reference address field depends on its highest bit:
+-+--------------+--------+------+-+-------------------------+ | | | | |0| Address within first64K words| |*| Op Code | R | X +-+-------------------------+ | | | | |1| Lower16 bits of address | +-+--------------+--------+------+-+-------------------------+ bit0 ... ...
When this high bit is zero, the lower sixteen bits correspond to an address inside the initial64K words; if set to one, these bits represent an offset within a64K-word section defined by bits42-47 of the Program Status Doubleword, combined to form the complete physical address.
CPU
The Sigma series demonstrated a performance increase of approximately twofold from the Sigma5 through to the Sigma9 Model3. For example, fixed-point multiplication times decreased from 7.2 μs to 3.8 μs, while floating-point division times improved from 30.5 μs down to 17.4 μs.
Most configurations incorporated at least two sets of 16 general-purpose registers. Context switching was streamlined by the LPSD instruction, which swapped register sets without the need for saving or restoring them, thereby boosting processing efficiency.
Memory
Sigma systems allowed memory addressing at various granularities: bytes, halfwords, words, or doublewords.
Except for the Sigma 5 and Sigma 8, all 32-bit Sigma models employed a memory map mechanism to implement virtual memory. Taking the Sigma 9 as an example, its effective virtual address spans 17 bits. Addresses from 0 to 15 directly reference general-purpose registers and are excluded from mapping. When operating in virtual memory mode, the upper eight bits (virtual page number) select one of 256 memory map registers, each 13 bits in length. These bits combined with the remaining nine bits produce the actual physical memory address.
Protection of access rights is managed through a separate set of 256 two-bit access control codes per virtual page (totaling 512 words), which govern permissions such as read, write, execute, or deny access. Furthermore, an additional array of 256 two-bit access control registers covers the initial 128k words of physical memory, functioning like a "lock-and-key" system using bits within the program status doubleword (PSD). Memory pages can be designated as "unlocked" or require a matching key within the PSD to permit access.
Diagnostic facilities
Sigma machines utilized PT16B power supplies capable of ±5% voltage adjustments to facilitate component testing and maintenance procedures. The control panel also allowed modifications to clock speeds for diagnostic purposes.
The Sigma 9 included "SNAP" registers that captured internal CPU status at every clock cycle. Key diagnostics relied on "Snap Data" tapes that enabled stepwise replay of instructions alongside comparisons with expected outcomes. This approach allowed pinpointing faults down to individual register bits, significantly accelerating hardware troubleshooting.
Peripherals
Input and output operations were controlled by Input-output processors (IOPs), each providing an 8-bit data pathway to main memory. Systems could accommodate up to eight IOPs, with each supporting connections to as many as 32 device controllers.
Two types of IOPs were available: selector IOPs (SIOP) and multiplexer IOPs (MIOP). SIOPs delivered data transfer rates up to 1.5 megabytes per second but permitted only one device active at any moment. In contrast, MIOPs supported simultaneous operation of up to 32 devices at a combined rate of approximately 0.3 MBPS, optimized for slower peripheral devices.
Mass storage
The principal mass storage device was known as a RAD (random-access disk), characterized by having 512 fixed read/write heads and a vertically mounted disk approximately 600 mm (24 inches) in diameter rotating at relatively low speeds. This fixed head design facilitated rapid data access. Storage capacities ranged from about 1.6 to 6.0 megabytes for temporary storage needs, whereas larger multi-platter disks provided permanent storage solutions.
| Device | Device type | Capacity [MB] | Avg seek time [ms] | Avg rotational delay [ms] | Avg transfer rate [kB/s] |
|---|---|---|---|---|---|
| 3214 | RAD | 2.75 | N/A | 8.5 | 647 |
| 7202 | RAD | 0.7 | N/A | 17 | 166 |
| 7203 | RAD | 1.4 | N/A | 17 | 166 |
| 7204 | RAD | 2.8 | N/A | 17 | 166 |
| 7232 | RAD | 6.0 | N/A | 17 | 355 |
| 3231 | Cartridge disk | 2.4 removable | 38 | 12.5 | 246 |
| 3232 | Cartridge disk | 4.9 removable | 38 | 12.5 | 246 |
| 3233 | Cartridge disk | 4.9 fixed / removable | 38 | 12.5 | 246 |
| 3242 | Cartridge disk | 5.7 removable | 38 | 12.5 | 286 |
| 3243 | Cartridge disk | 5.7 fixed / removable | 38 | 12.5 | 286 |
| 7251 | Cartridge disk | 2.3 removable | 38 | 12.5 | 225 |
| 7252 | Cartridge disk | 2.3 fixed / removable | 38 | 12.5 | 225 |
| 3277 | Removable disk | 95 | 30 | 8.3 | 787 |
| 7271 | Removable disk | 46.8 | 35 | 12.5 | 245 |
Communications
The Sigma 7611's Character Oriented Communications module (COC) accommodates between one and seven Line Interface Units (LIUs), with each LIU supporting one to eight line interfaces functioning in simplex, half-duplex, or full-duplex configurations. This subsystem is optimized for character-based data transfer at low to moderate speeds.
An optional Communication Input/Output Processor (CIOP) could manage as many as 128 communication lines, operating at baud rates ranging from 128 to 9600. It utilized dedicated mainframe memory for control functions and line status tracking, thereby improving communication performance in enterprise environments.
System control unit
The System Control Unit (SCU) was a microprogrammable processor engineered to connect with a Sigma CPU, peripherals, analog devices, and multiple line protocols. It processed horizontal microinstructions with a word size of 32 bits. Developers could create SCU microprograms using a cross-assembler executed on a Sigma platform.
Carnegie Mellon Sigma 5
Donated to the Computer History Museum in 2002, Carnegie Mellon University’s Sigma 5 system consists of five full-sized cabinets accompanied by a monitor, control panel, and printer. It is believed to be the last fully operational Sigma 5 unit.
The Sigma 5 was initially offered at a price of US$300,000, featuring 16 kilowords of magnetic-core memory. An upgrade to 32 kilowords was available for an additional $50,000. Its hard disk drive capacity reached 3 megabytes.
Operating systems
Neither the Sigma 5 nor the Sigma 8 included memory mapping capabilities but supported Basic Control Monitor (BCM) and Batch Processing Monitor (BPM). The Sigma 8 additionally ran Real-time Batch Monitor (RBM) alongside BPM/BTM.
Subsequent models started with BPM augmented by a timesharing extension known as BTM; together these were referred to as BPM/BTM. The Universal Time-Sharing System (UTS), introduced in 1971, provided enhanced time-sharing functionality. Its successor, Control Program V (CP-V), released in 1973, incorporated real-time processing, remote batch operations, and transaction management. The Sigma 9 featured a dedicated real-time operating system called Control Program for Real-Time (CP-R). Xerox Operating System (XOS), designed as an IBM DOS/360 alternative for Sigma 6/7/9 models, experienced limited adoption.
Third party operating systems
Available third-party operating systems included GEM (Generalized Environmental Monitor), characterized as UNIX-like, and JANUS from Michigan State University, which offered adaptable real-time timesharing features.
Applications software
Xerox’s CP-V software suite from 1978, referred to as processors, encompassed essential business applications such as:
- Terminal Executive Language (TEL) and Control Command Interpreter (CCI) for command execution and batch processing
- File management tools supporting backup and restoration
- EASY, an interactive debugger for Fortran and BASIC
- Extended FORTRAN IV, Meta-Symbol macro assembler, AP assembler, BASIC, FLAG (FORTRAN Load and Go), ANS COBOL, APL, RPG
- TEXT word processing and Simulation Language (SL-l)†
- LINK and LOAD loaders with LYNX interface
- GENMD load module editor alongside DELTA machine language debugger
- FORTRAN Debug Package (FDP), COBOL On-line Debugger, and EDIT text editor
- Peripheral Conversion Language (PCL) facilitating data format conversion
- Service utilities including SYSGEN system generation, ANLZ dump analysis, and library maintenance
- Sort/Merge utilities and EDMS database management†
- GPDS General Purpose Discrete Simulator†, CIRC circuit analysis†, and MANAGE file/report generation system†
†These were commercial software products requiring purchase.
Operating systems
The Basic Control Monitor (BCM) designed for the Sigma 2 and Sigma 3 provided comprehensive real-time processing capabilities alongside background batch operations; additionally, the Sigma 3 included support for RBM.
Clones
After Honeywell ceased production of Sigma hardware—originally acquired primarily from Xerox in 1975—various manufacturers developed systems compatible with Sigma. The Telefile T-85, introduced in 1979, served as a drop-in replacement for 32-bit Sigma machines, maintaining upward compatibility. Ilene Industries Data Systems unveiled the MOD 9000, a clone of the Sigma 9 featuring a distinct I/O design. Realtime Computer Equipment produced the RCE-9, which offered upward compatibility and support for IBM peripherals. The Modutest Mod 9, created under the leadership of Gene Zeitler (President), Lothar Mueller (Senior Vice President), and Ed Drapell, achieved full hardware and software compatibility with the Sigma 9; its clientele included Telefile, Utah Power and Light, Minnesota Power, Taiwan Power, and the Ohio College Library Center (OCLC). In France, CII manufactured clones of the Sigma 7 series known as the CII 10070, Iris 50, and Iris 80.
By 2023, the SIMH emulator had incorporated support for Sigma 5, Sigma 6, and Sigma 7 platforms, with CP-V version F00 available for emulation purposes.
See also
Further reading
External links
- Online systems at Living Computers: Museum + Labs, showcasing the Paul Allen collection of timesharing and interactive computers, including a Xerox Sigma 9 running CP-V.