Scientific Micro Systems

Signetics
Company type	Subsidiary (historically)
Industry	Semiconductor
Founded	1961
Fate	Acquired product rights for SMS 300 in 1978
Headquarters	Sunnyvale, United States
Products	Microprocessors, microcontrollers (including 8X300 series)

Adapted from the English Wikipedia article Scientific Micro Systems, available under CC BY-SA 4.0Updated 8 August 2025

The 8X300 microprocessor was introduced by Signetics in 1976 as a secondary source for the SMS 300, originally created by Scientific Micro Systems, Inc. Although SMS was responsible for its design, Signetics held exclusive manufacturing rights and fully acquired the product in 1978, subsequently renaming it the 8X300.

Engineered as a rapid microcontroller and signal processor, the 8X300 incorporated bipolar Schottky transistor technology, which allowed it to fetch, decode, and execute instructions within a mere 250 ns. Its design enabled data to be received from one peripheral, processed internally, and sent out to another device all during a single instruction cycle—a capability that set it apart from typical NMOS microprocessors available at the time.

In 1982, Signetics released an improved version called the 8X305. This model found significant use in military applications and was also second-sourced by Advanced Micro Devices under the designation AM29X305. Later on, production rights were transferred to Lansdale Semiconductor Inc., which maintained manufacturing of the 8X305. Additionally, a Soviet-produced equivalent was manufactured under the name KM1818VM01 ().

Architecture

Encased in a 50-pin DIL ceramic housing, the device operates from a single 5V power supply. An external pass transistor works alongside an integrated voltage regulator on the chip to deliver a regulated 3V to certain internal sections, keeping total current consumption below 450mA.

Clock signals are generated either by connecting an 8 MHz crystal oscillator across two pins or by supplying two out-of-phase signals from an external clock source.

One notable characteristic is its dedicated 13-bit address bus combined with a 16-bit data bus specifically for program memory access. This configuration supports direct addressing of up to 8192 program words of 16 bits each, allowing direct attachment of ROM or PROM devices without additional interfacing hardware.

A separate multiplexed 8-bit address/data bus known as the Interface Vector (IV) bus manages both data transfer and input/output operations. The status of this bus is governed by two control signals: WC (write command) and SC (select command), which define three operational modes:

SC=1, WC=0: outputs I/O address
SC=0, WC=1: outputs I/O data
SC=0, WC=0: expects I/O input

Two additional control lines, LB (left bank select) and RB (right bank select), effectively double the IV bus addressable space, typically toggling between RAM and I/O port access.

Distinct from many microprocessors that perform mask, rotate, shift, and merge functions within a single arithmetic logic unit (ALU), the 8X300 utilizes separate dedicated units for each operation. This architecture allows simultaneous rotation, masking, modification, shifting, and merging of data within one instruction cycle.

Instruction set

The processor primarily manipulates 8-bit data units but employs a mask unit capable of handling individual or multiple bits, making it adept at variable-length data processing. Internally, it contains eight general-purpose 8-bit read/write registers labeled R1 through R6 and R9, along with an auxiliary register (R0) used to store one operand in two-operand instructions such as ADD or AND. A single-bit overflow register (R8) retains carry bits generated during ADD operations. Two virtual write-only registers—IVL (R7) and IVR (R15)—place addresses onto the IV bus. Furthermore, two groups of eight virtual registers each (R16-R23 and R24-R31) facilitate data transfers to and from the IV bus. The upper two bits select either left or right bank while the lower three bits specify rotation or shift amounts. An 8-bit buffer on the IV bus holds recently transferred data to support merge operations.

Instruction opcodes are determined by the three highest-order bits and are categorized into eight distinct classes:

MOVE: transfers register contents; outputs or reads data on/from the IV bus; or moves data between IV buses.
ADD, AND, XOR: combine values from the auxiliary register with another register before performing a MOVE.
XEC: executes an instruction located at a different local address without advancing the program counter.
NZT: implements conditional branching based on register values.
XMIT: loads an 8-bit binary pattern into either a register or onto the IV bus.
JMP: carries out unconditional jumps within the full range of program memory (8192 words).

The bit allocation within instructions varies depending on opcode type:

For MOVE, AND, ADD, and XOR, five bits designate the source register; three bits specify rotation/mask operations (the R/L field); five bits identify the destination register.
For XEC and NZT, five bits indicate source register; remaining eight bits form an address field.
- In XEC, contents of the source register are added to this address field to generate the lower eight bits of the target program address.
- In NZT, if the source register is non-zero, branching occurs using this address field as lower eight bits of program memory.
For XMIT, five bits specify destination register; remaining eight bits represent immediate data.
For JMP, all thirteen bits correspond directly to an absolute program memory address.

Shift, rotate, mask and merge

Situated between the register bank and the ALU, the rotate and mask units facilitate data manipulation prior to ALU operations:

Rotate Unit: performs rightward rotation of data by the amount specified in the opcode.
Mask Unit: clears the upper bits, preserving only the lower bits as indicated by the opcode.

Between the ALU and the IV bus, the Shift and Merge units handle data modification before output:

Shift Unit: shifts data left by a number of positions defined by the opcode.
Merge Unit: substitutes bits within the IV-bus buffer according to the opcode before transmission; if the count is zero, it replaces all 8 bits.

Instruction combinations differ depending on source and destination:

MOVE, ADD, AND, XOR:
- register-to-register transfers (including IVL/IVR): apply rotation
- register to IV bus output: utilize shifting and merging
- IV-bus input to register: employ rotation and masking
- IV-bus input to IV-bus output: combine rotation, masking, shifting, and merging
- IV-bus input to IVL/IVR (address output): use rotation and masking
XEC and NZT: rotate and mask operations are applied to IV-bus input
XMIT: applies shift and merge on IV-bus data output

I/O

Data exchange with the 8X300 occurs in two phases: 1. Instructions such as MOVE, ADD, AND, XOR, or XMT targeting virtual registers IVL or IVR generate an address on the IV bus accompanied by Select Command and Bank Select signals. Addressing may be required for both banks. I/O ports latch this address through decoders/latches or integrated devices like the 8X32. Once latched, ports remain active until a new address is issued, allowing multiple accesses without repeated addressing. Two I/O ports or RAM addresses can be simultaneously active, with rapid switching enabled by Bank Select signals. 2. The actual data transfer uses any instruction except JMP, designating registers R16–R31 as source or destination; these registers determine which Bank Select signal is engaged.

Applications

Signetics showcased the 8X300 functioning as a floppy disk controller, later integrated with the 8X330. Additional application notes described its use in teletype multiplexers, data concentrators, remote terminal controllers, computer I/O bus emulators, and RAM interface designs.

A portable demonstration system highlighted its role in traffic light control.

Olivetti utilized both the 8X300 and 8X305 as controllers for ST506 hard disks within their M20 PC series.

Convergent Technologies incorporated the 8X300 family into their AWS hard disk controllers released in 1981.

Western Digital employed the 8X300 in their WD1000 ST506 controller and used the 8X305 in their WD1001 ECC hard disk controller.

Support devices

8X01: Cyclic redundancy check unit
8X31 / 8T31: 8-bit latched bidirectional I/O port
8X32 / 8X36 / 8X42: 8-bit latched addressable bidirectional I/O port
8T39: Addressable bus expansion device
8X41: Asynchronous bidirectional bus extender and repeater (SABER)
8T58: Transparent bus expansion device
8X320: Bus interface register array
8X330: Floppy disk formatter/controller unit
8X350: Bipolar RAM with 2048 bits (256×8) featuring a 35 ns access time
SMS360 / 8X360: Interface vector byte device

External links