StrongARM

StrongARM
Company type	Microprocessor series
Industry	Semiconductor
Predecessor	DEC Alpha (initial concept)
Founded	1995
Founder	Digital Equipment Corporation
Fate	Acquired by Intel in 1997; replaced by XScale in early 2000s
Headquarters	Palo Alto, California and Austin, Texas, United States
Products	StrongARM microprocessors (SA-110, SA-1100, SA-1110, SA-1500)

The StrongARM series consists of microprocessors developed by Digital Equipment Corporation during the late 1990s, implementing the ARM v4 instruction set architecture. In 1997, Intel acquired this technology from DEC's Digital Semiconductor division as part of a patent infringement lawsuit resolution. Intel continued production before eventually replacing StrongARM with the ARM-based architecture known as XScale in the early 2000s.

History

Allen Baum has indicated that StrongARM originated from efforts to create a low-power variant of the DEC Alpha, which ultimately proved impractical. DEC then shifted focus toward low-power designs, choosing to adopt the ARM architecture. At that period, one prominent user of ARM technology was Apple, whose Newton device was based on ARM processors. DEC approached Apple about developing a high-performance ARM chip, and Apple showed interest provided such performance levels could be realized.

StrongARM emerged as a joint venture between DEC and Advanced RISC Machines to develop a faster ARM microprocessor aimed at the higher end of the low-power embedded market segment. The goal was to serve devices requiring greater performance than conventional ARM chips could deliver, including advanced personal digital assistants and set-top boxes.

DEC’s semiconductor arm, traditionally located in Massachusetts, established a design center in Palo Alto, California to tap into Silicon Valley expertise. This facility, led by Dan Dobberpuhl, served as the main design site for StrongARM. Additionally, a team in Austin, Texas, comprised of former DEC engineers returning from stints at Apple Computer and Motorola, also contributed to development. The project kicked off in 1995 and rapidly produced its initial design, the SA-110.

In 1997, as part of a legal settlement, DEC transferred StrongARM to Intel. Intel utilized StrongARM to supplant its waning RISC processors, specifically the i860 and i960. Following this transition, many Palo Alto engineers moved on to start-ups such as SiByte, which specialized in MIPS system-on-chip (SoC) solutions for networking applications. Meanwhile, the Austin team founded Alchemy Semiconductor, focusing on MIPS SoCs designed for handheld devices. Intel subsequently introduced an evolved StrongARM core under the name XScale in 2000.

SA-110

The SA-110 represented the inaugural microprocessor within the StrongARM lineup, initially available at clock speeds of 100, 160, and 200 MHz when announced on February 5, 1996. Sample units were immediately accessible, with mass production targeted for mid-1996. Later that year, enhanced versions running at 166 and 233 MHz were launched, with manufacturing planned for December 1996. Throughout 1996, the SA-110 dominated performance metrics among processors intended for portable devices and became a pivotal CPU for internet/intranet appliances as well as thin client systems. Its first significant design adoption was in the Apple MessagePad 2000. Other prominent implementations included the Acorn Risc PC and Eidos Optima video editing workstation. The principal designers behind this processor were Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.

Description

The SA-110 utilized a straightforward scalar microarchitecture featuring in-order instruction execution and a traditional five-stage RISC pipeline. It was organized into several functional units: IBOX (responsible for instruction fetching, decoding, and issuing), EBOX (housing execution units), IMMU and DMMU (instruction and data memory management units), BIU (bus interface unit), WB (write buffer), and PLL (phase-locked loop for clock generation). The IBOX converted complex ARM instructions into simpler micro-operations but did not include branch prediction hardware, instead depending on rapid branch handling mechanisms.

Execution took place within the EBOX, which incorporated a register file with three read ports and two write ports, an arithmetic logic unit (ALU), a barrel shifter—both capable of single-cycle operation—a non-pipelined multiplier with multiple cycle latency, and condition code evaluation logic. Both the IMMU and DMMU contained 32-entry fully associative translation lookaside buffers (TLBs) that supported various page sizes. The write buffer accommodated eight entries of 16 bytes each to enable pipelining of store instructions.

Clock signals inside the chip were generated by the PLL from an external 3.68 MHz reference; this component was manufactured externally by CSEM in Switzerland. Instruction and data caches each measured 16 KB with 32-way set associativity and were virtually addressed to maximize cache hit rates when paired with slower, economical memory—a deliberate design aimed at boosting performance while managing costs. These caches consumed approximately half of the processor’s silicon area and represented the majority of its transistor count.

Produced using DEC’s proprietary CMOS-6 fabrication process at Fab 6 in Hudson, Massachusetts, the SA-110 integrated 2.5 million transistors on a die measuring 49.92 mm² (7.8 mm by 6.4 mm). The CMOS-6 process featured a 0.35 μm technology node with three layers of aluminum interconnect specifically optimized for this design. The processor operated on a variable voltage supply ranging from 1.2 to 2.2 volts to optimize power efficiency versus performance trade-offs and was housed in a 144-pin thin quad flat pack (TQFP).

SA-1100

Derived from DEC’s SA-110 and introduced in 1997, the SA-1100 targeted handheld devices such as PDAs. It featured a smaller 8 KB data cache to make room for integrated controllers including memory management, PCMCIA interface, and color LCD support connected via an on-chip system bus, alongside five serial I/O channels linked to a peripheral bus. Its memory controller was compatible with FPM and EDO DRAM, SRAM, flash memory, and ROM. The PCMCIA controller supported two slots sharing the memory address and data buses, necessitating additional glue logic. Serial I/O included interfaces such as a slave USB port, SDLC protocol support, two UARTs, an IrDA interface, MCP, and synchronous serial communication.

Intel introduced the SA-1101 companion chip in October 1998 to complement the SA-1100 by adding peripherals including video output, two PS/2 ports, a USB controller, and a PCMCIA controller that replaced the one integrated into the SA-1100. Initially designed by DEC but finalized by Intel following its acquisition of DEC’s Hudson fabrication facility, the SA-1101 expanded the feature set for devices based on the SA-1100.

The SA-1100 chip contained 2.5 million transistors on a die sized at 75.15 mm² fabricated using a 0.35 μm CMOS process technology and was packaged in a 208-pin TQFP format. Notable early implementations included devices like the Psion netBook and Psion Series 7.

SA-1110

Intel developed the SA-1110 as an alternative to the SA-1100, announcing it in March 1999 with samples available mid-year and ramping up volume production later that year before discontinuing it in early 2003. This processor was offered in clock speeds of either 133 MHz or 206 MHz supporting SDRAM running at 66 MHz or 103 MHz respectively. Its companion peripheral chip was designated as the SA-1111.

Encased in a 256-pin micro ball grid array package, the SA-1110 powered various mobile devices including PDAs such as Compaq/HP iPAQ models and HP Jornada series, Sharp SL-5x00 Linux-based platforms, as well as the Simputer device. It also served as the core processor for Intel’s Web Tablet—a pioneering large-screen portable web browsing product that was ultimately canceled shortly before its intended launch in 2001.

SA-1500

The SA-1500, derived from DEC's SA-110, was designed specifically for the set-top box segment. While DEC produced it in limited quantities, Intel never manufactured this chip. It operated within a frequency range of 200 to 300 MHz. This processor incorporated an upgraded SA-110 core, an integrated Attached Media Processor (AMP), and built-in controllers for SDRAM and I/O buses. The SDRAM controller was compatible with 100 MHz SDRAM modules, and the I/O controller handled a 32-bit bus operating at speeds up to 50 MHz, supporting peripheral devices as well as the SA-1501 companion chip.

The AMP utilized a 64-bit long instruction word architecture tailored for multimedia processing, encompassing integer and floating-point multiply–accumulate functions along with SIMD arithmetic capabilities. It accessed data from a 64-entry register file with 36-bit width and included control registers. Sharing the data cache with the SA-110 core via an internal bus, the AMP contained an ALU with shifter, branch unit, load/store unit, multiply–accumulate unit, and a single-precision floating-point unit. Additionally, it allowed for user-defined instructions through a writable control store consisting of 512 entries.

The complementary SA-1501 chip enhanced video and audio processing capabilities while providing expanded I/O options such as PS/2 ports, parallel port, and other peripheral interfaces.

Built with 3.3 million transistors on a 60 mm² die using a 0.28 μm CMOS fabrication process, the SA-1500 operated on an internal voltage supply between 1.5 and 2.0 V with a 3.3 V supply for I/O. Its power consumption varied from less than 0.5 W at 100 MHz to approximately 2.5 W when running at 300 MHz. Packaging options included a 240-pin metal quad flat package or a 256-ball plastic ball grid array.

StrongARM latch

The StrongARM latch is a latch circuit design initially introduced by Toshiba engineers led by Tsuguo Kobayashi et al. It became well-known through its implementation in StrongARM processors and is extensively used in integrated circuits as a sense amplifier, comparator, or as a highly sensitive and robust latch.