Jump to content

UNIVAC II

From Alfawiki
UNIVAC II
Company typeComputer system
IndustryComputing
PredecessorUNIVAC I
Founded1958
FounderUNIVAC branch of Sperry Rand
ProductsComputer systems

The UNIVAC II system, introduced in 1958 by the UNIVAC branch of Sperry Rand, represented a significant upgrade over the original UNIVAC I. It featured an expanded core memory capacity, increasing from 2,000 to 10,000 words, and utilized enhanced UNISERVO II tape drives compatible with both metal tapes and newly introduced PET tape media. While it incorporated certain transistorized components, the machine largely relied on vacuum tube technology. Importantly, the UNIVAC II preserved full backward compatibility with software developed for the UNIVAC I and had an approximate weight of .

Overall system circuit components

Vacuum tubes 5,200
Tube varieties 20
Crystal diodes 18,000
Magnetic cores 184,000
Transistors 1,200
Distinct cabinets 4

The numbers provided are estimates and do not include peripherals related to input-output functions.

Programming architecture and numeric representation

Internal numeric format Binary coded decimal (BCD)
Decimal digits per memory word 12
Decimal digits per instruction 6
Instructions contained per word 2
Number of decoded instructions utilized 54
Arithmetic format Fixed-point arithmetic
Instruction format Single-address instructions

The decimal point is fixed immediately after the sign digit.

Arithmetic processing unit

Construction technology Vacuum tubes
Arithmetic operation mode Serial processing
Timing method Synchronous timing
Including memory access (microseconds) Excluding memory access (microseconds)
Addition operation 160 120
Multiplication operation 1,720 1,680
Division operation 3,030 2,990

Typical execution times (in microseconds):

Addition or subtraction (11-digit operands) | 200 Multiplication (11-digit operands) | 1,900 Division (11-digit operands) | 3,700 Comparison (12-digit operands) | 200 Data transfer (between memory and register) | 40 per word + 80 per instruction

These instruction durations encompass both fetching and execution phases with minimal delay.

Magnetic core memory details

Memory capacity | 10,000 words; equivalent to 120,000 characters Memory address range | Locations from 0000 to 1999 Access timing | Zero wait time (memory references start during "Time Out") Basic cycle time | 20 microseconds Physical construction | Composed of 42 magnetic core planes; each plane measures a grid of 50 by 80 cores

The standard user memory consists of a magnetic-core unit with a capacity of 2,000 words divided into two segments per plane. Each plane stores two bits per word across all words. Physically, the memory forms a rectangular solid .

Addressing memory entails selecting two cores in each plane by intersecting specific rows and columns across all planes. A temporary half-word insertion register holding 42 bits is used during read/write operations. Writing data involves sequentially transferring bits from this register to the upper and lower parts of the selected cores; reading reverses this sequence.

Memory speed is synchronized with the arithmetic unit’s timing, allowing transfer of twelve characters within 40 microseconds through serial-to-parallel conversion facilitated by a high-speed bus and the insertion register.

Feature Verification

Registers and circuits are commonly duplicated, with their contents constantly compared to identify errors. If discrepancies are found, the system halts operation to prevent further issues, allowing instructions to be retried. The Univac System employs a pulse code method that ensures every character contains an odd number of pulses; characters are verified at critical points, and the system pauses if an even pulse count is detected. Additional error detection circuits cause system stalls for other fault types.

Errors arise when an invalid memory address is accessed. During data transfer from rI to rM, an odd-even error stops the transfer and pinpoints the fault location, while a modulus 100 counter displays a 720-character count.

"All ones" validation

In addition to parity bit verification on the high-speed bus, a secondary mechanism prevents the formation of the invalid "all ones" character caused by hardware malfunctions. Input/output checkers also identify this erroneous character.

Integrated checking capabilities are present in the Card-to-Tape Converter, Tape-to-Card Converter, and High Speed Printer units.

Fusing System

The Univac system is comprehensively fused to enable effective fault isolation. Each bay contains individual fuses along with main fuses on all DC and AC power lines. When a fuse blows, power is cut off, an indicator highlights the affected bay, and a "flag" signals the exact fuse involved.

Voltage Surveillance

A continuous automatic voltage monitoring system observes essential DC voltages and activates alarms if any voltage strays beyond predefined thresholds.