Unibus
| Industry | Computer hardware |
|---|---|
| Founded | May 16, 1957 in Maynard, Massachusetts, United States |
| Headquarters | Maynard , United States |
Key people | Gordon Bell, Harold McFarland |
The Unibus represents the initial implementation among various computer bus and backplane architectures utilized in PDP-11 and early VAX machines developed by Digital Equipment Corporation (DEC) based in Maynard, Massachusetts. Conceived circa 1969 by Gordon Bell and Harold McFarland at Carnegie Mellon University, the Unibus combined the roles of system and peripheral buses into a single unified interface. This consolidation facilitated direct memory access (DMA) for connected peripherals and streamlined the creation of device drivers through memory-mapped I/O techniques.
Although physically extensive, the Unibus was later replaced by the more space-efficient Q-bus, which reduced pin requirements by multiplexing signals. For enhanced performance, certain PDP models incorporated Fastbus, effectively consisting of two Unibusses operating in tandem, while subsequent VAX and PDP-11 generations adopted Massbus, a specialized bus dedicated to input/output operations.
Technical specifications
The Unibus consists of 72 signal lines, commonly routed via two 36-pin edge connectors on each circuit board. When excluding power and ground connections, it functions as a 56-line bus. Each segment supports up to 20 devices, with multiple segments interconnected through bus repeater units.
Engineered as a fully asynchronous bus, it supports devices operating at varying speeds and permits arbitration overlap during data exchange processes. Its 18 address lines allow access to a maximum of 256 KB of memory space, with the uppermost 8 KB typically allocated for memory-mapped I/O registers within PDP-11 systems.
To reduce redundant circuitry, complex asynchronous transfer logic is primarily embedded within master devices, which are fewer in number compared to slave devices. The intricacies of interrupt management are centralized within the processor responsible for handling interrupts, enabling most I/O controllers to utilize relatively simple logic implemented via custom MSI integrated circuits.
Pinout
| Number | Name | Type | Description |
|---|---|---|---|
| 18 | A00-A17 | 1 | Address Lines |
| 16 | D00-D15 | 1 | Data Lines |
| 4 | BR4-BR7 | 1 | Bus (Interrupt) Requests with priorities ranging from 4 (lowest) to 7 (highest) |
| 4 | BG4-BG7 | 2 | Bus (Interrupt) Grants corresponding to priorities 4 through 7 |
| 1 | NPR | 1 | Non-Processor (DMA) Request |
| 1 | NPG | 2 | Non-Processor (DMA) Grant |
| 1 | MSYNC | 1 | Master Synchronization Signal |
| 1 | SSYNC | 1 | Slave Synchronization Signal |
| 1 | BBSY | 1 | Bus Busy Indicator |
| 1 | SACK | 1 | Selection Acknowledge Signal |
| 1 | INIT | 1 | Bus Initialization Signal |
| 1 | INTR | 1 | Interrupt Request Line |
| 1 | PA | 1 | Parity Control Line A |
| 1 | PB | 1 | Parity Control Line B |
| 2 | C0-C1 | 1 | Control Lines |
| 1 | ACLO | 3 | AC Power Low Indicator |
| 1 | DCLO | 3 | DC Power Low Indicator |
| 2 | +5v | - | Power Supply Lines (not counted among the 56) |
| 14 | Gnd | - | Ground Connections (excluded from the 56) |
Lines classified as Type 1 employ a multi-transmitter wired-OR configuration with pull-up resistors installed on terminator cards to ensure signal stability.
Type 2 signals are conditionally forwarded by each card; when the SACK line is asserted, the grant signal is held and not propagated further. Slots without cards require "grant continuity cards" to preserve signal continuity across the bus.
Type 3 signals originate directly from the power supply unit and serve to notify devices of impending power loss, allowing orderly shutdown procedures to avoid data loss or corruption.
The two control lines labeled C0 and C1 select among four distinct data transfer cycles:
- DATI (Data In – read operation)
- DATIP (Data In/Pause – initial phase of Read-Modify-Write cycle, finalized by DATO or DATOB)
- DATO (Data Out – full word write)
- DATOB (Data Out/Byte – byte-level write)
An additional interrupt cycle facilitates automatic transfer of an interrupt vector from the requesting device to the processor responsible for servicing interrupts.