Zero ASIC
| Company type | Private |
|---|---|
| Industry | Semiconductor |
| Predecessor | Adapteva, Inc. |
| Founded | March 2008 |
| Founder | Andreas Olofsson |
| Fate | Renamed from Adapteva, Inc. |
| Headquarters | Lexington, Massachusetts , United States |
Area served | Worldwide |
Key people | Andreas Olofsson (Founder) |
| Products | Epiphany multi-core MIMD architecture processors, Parallella single-board computer |
Zero ASIC Corporation, previously known as Adapteva, Inc., operates as a fabless semiconductor firm focused on designing low-power many-core microprocessors. It was among the pioneers in unveiling a design integrating 1,000 specialized processing cores within a single chip.
Established in March 2008 by entrepreneur Andreas Olofsson, the company set out to achieve a tenfold enhancement in floating-point performance per watt tailored for mobile devices. Their technology is based on the Epiphany multi-core MIMD architecture and gained widespread recognition through the Parallella Kickstarter campaign initiated in September 2012, which aimed to democratize access to supercomputing.
History
In October 2009, Adapteva raised $1.5 million in Series A funding from BittWare after developing a 16-core prototype fabricated with 65 nm technology that showcased its massively parallel design. The firm began distributing samples of its initial commercial chip in May 2011 and revealed intentions to expand the core count up to 4,096 on a single integrated circuit.
By October 2011, Adapteva launched the Epiphany III chip produced using both 28 nm and 65 nm fabrication processes, reinforcing its position in the market for energy-efficient multi-core processors.
Products
The flagship product range from Adapteva centers on the Epiphany scalable multi-core MIMD architecture. This architecture supports chips containing as many as 4,096 RISC out-of-order microprocessors sharing a unified 32-bit flat memory address space. Each core can operate at frequencies up to 1 GHz, achieving 2 GFLOPS (single-precision), and features a unified register file sized at 64×32 bits. The proprietary instruction set architecture is tailored for single-precision floating-point operations and can be programmed using ANSI C via a GNU-GCC based toolchain. Present designs allocate 32 KB of local memory per core for code execution, stack management, and most temporary data storage, while permitting access to other cores’ memory or external RAM with reduced speed.
Instead of conventional CPU cache hierarchies, the memory model resembles that of the Sony/Toshiba/IBM Cell processor but supports off-chip and inter-core load/store operations, easing software adaptation. This hardware-based partitioned global address space removes the need for complex cache coherency mechanisms, thereby overcoming scalability limits common in multicore processors. Inter-core communication is efficiently handled through an on-chip network that enables scalable message passing.
Scalability
The Epiphany architecture achieves extensive scalability through four e-links connecting multiple chips arranged in a grid topology, enabling systems composed of thousands of cores.
On August 19, 2012, Adapteva published detailed specifications for its Epiphany multi-core coprocessors.
| Technical details | E16G301 | E64G401 |
|---|---|---|
| Number of cores | 16 | 64 |
| Core frequency (MHz) | 1000 | 800 |
| Performance per core (GFLOPS) | 2 | 1.6 |
| Aggregate frequency (GHz) | 16 | 51.2 |
| Total performance (GFLOPS) | 32 | 102 |
| Die size (mm2) | 8.96 | 8.2 |
| Process node (nm) | 65 | 28 |
| Typical power consumption (W) | 0.9 | 1.4 |
| Maximum power consumption (W) | 2 | 2 |
In September 2012, the Epiphany-III (E16G301) was fabricated using a 65 nm process with an area of 11.5 mm² and operating at 500 MHz, while engineering samples of the Epiphany-IV (E64G401), featuring 64 cores, were produced using a GlobalFoundries 28 nm process running at 800 MHz.
The Epiphany architecture targets applications such as real-time facial and speech recognition on smartphones, energy-efficient exaflop-scale supercomputing platforms, and floating-point acceleration within FPGA-based embedded systems.
Parallella project
In September 2012, Adapteva introduced the Parallella initiative on Kickstarter, branding it as "A Supercomputer for everyone." To attract developer interest, the campaign released detailed architecture documentation. The funding target of $750,000 was achieved within 30 days, with supporters pledging a minimum of $99 to obtain a unit. Although the initial shipping date was set for May 2013, the first single-board computers powered by the 16-core Epiphany processor were ultimately delivered in December 2013.
The compact form factor of the board measures roughly . The Kickstarter effort accumulated $898,921 but did not reach the $3 million goal required for mass production of the 64-core Parallella model. Supporters who pledged over $750 were granted access to a limited-edition "parallella-64" prototype, produced from early wafer fabrication runs.
| Parallella-16 Micro Server | Parallella-16 Desktop Computer | Parallella-16 Embedded Platform | |
|---|---|---|---|
| Intended Use | Headless server with Ethernet connectivity | Desktop personal computer | High-end embedded applications |
| CPU | Dual-core 32-bit ARM Cortex-A9 with NEON at 1 GHz (Xilinx Zynq XC7Z010/020) | Dual-core 32-bit ARM Cortex-A9 with NEON at 1 GHz (Xilinx Zynq XC7Z020) | |
| Accelerator | 16-core Epiphany III multi-core coprocessor (E16) | ||
| RAM | 1 GB DDR3L memory | ||
| Network Interface | Gigabit Ethernet (10/100/1000 Mbps) | ||
| USB Ports | — | Two USB 2.0 ports (HS and OTG) | |
| Video Output | — | HDMI interface | |
| Storage Medium | 16 GB microSD card included | ||
| Expansion Options | — | Two eLinks plus 24 GPIO pins | Two eLinks plus 24 GPIO pins |
| FPGA Resources | 28K logic cells and 80 DSP slices | 80K logic cells and 220 DSP slices | |
| Weight | 36 grams (1.3 oz) | 38 grams (1.3 oz) | |
| Dimensions | 3.5 by 2.1 by 0.625 inches (88.9 mm × 53.3 mm × 15.9 mm) | ||
| Model Number | P1600-DK-xx | P1601-DK-xx | P1602-DK-xx |
| HTS Classification | 8471.41.0150 | ||
| Power Supply | Powered via USB (2.5 W) or external 5 V DC (~5 W) | ||
This initiative highlights Adapteva's approach to entering sectors requiring power-efficient parallel computing by offering cost-effective hardware combined with a collaborative development community.
Epiphany V
By 2016, Adapteva had engineered a 1024-core version of the Epiphany architecture featuring 64-bit capabilities, larger local memory (64 KB), support for 64-bit addressing, double-precision floating-point operations, SIMD single-precision instructions, and 64-bit integer processing. This iteration was fabricated using a 16 nm technology node and incorporated instruction set improvements aimed at enhancing deep learning and cryptographic workloads. In July 2017, following the appointment of Adapteva’s founder as a DARPA MTO program manager, it was announced that Epiphany V was "unlikely" to be commercially launched.
Performance
The Parallella board with its 16 cores achieves around 5.0 GFLOPS per watt, whereas the 64-core Epiphany-IV chip (manufactured on a 28 nm process) attains an estimated efficiency of approximately 50 GFLOPS per watt for single-precision calculations. A cluster composed of thirty-two such boards can deliver up to 15 GFLOPS per watt. For comparison, leading GPUs from AMD and Nvidia during the years spanning 2009 to 2011 offered roughly 10 GFLOPS per watt in energy efficiency.
See also
- Asynchronous array of simple processors
- SW26010 – Chinese-designed architecture powering the Sunway TaihuLight supercomputer
- Vision Processing Unit – processors with similar capabilities
Further reading
- Linley Gwennap, Adapteva: Enhancing Floating-Point Performance with Lower Power Consumption. Epiphany as a Floating-Point Accelerator for Mobile Devices. // Microprocessor Report, June 2011