Alpha 21364

Digital Equipment Corporation
Industry	Computer hardware
Fate	Acquired by Compaq Computer Corporation
Key people	Richard L. Sites (co-lead of Alpha architecture definition)
Products	Alpha 21364 microprocessor

Alpha 21364, internally referred to as "Marvel" and also identified as EV7, is a microprocessor created by Digital Equipment Corporation (DEC), which was subsequently acquired by Compaq Computer Corporation. This processor implements the Alpha instruction set architecture (ISA).

History

Unveiled by Compaq during the 11th Annual Microprocessor Forum in October 1998, the Alpha 21364 represented an upgraded version of the Alpha 21264. Its enhancements included an on-chip secondary cache of 1.5 MB with 6-way set associativity, an integrated Direct Rambus DRAM memory controller, and a network controller designed for inter-processor communication. Key improvements to the core involved expanding the victim buffer fourfold to 32 entries (split evenly between Dcache and Scache), slight refinements to the branch predictor, and increasing the miss buffer size to 16 entries.

Initially planned for tape-out by late 1999, with prototype samples expected in early 2000 and mass production slated for late 2000, the schedule slipped, resulting in tape-out only being completed in April 2001. The processor officially launched on January 20, 2002, powering systems such as the AlphaServer ES47, ES80, and GS1280 at frequencies ranging from 1.0 to 1.25 GHz. Unlike its predecessors, the Alpha 21364 was not made available for general commercial sale.

The next-generation Alpha 21464 (EV8), which was designed to support four-way simultaneous multithreading (SMT), was introduced in October 1999 but ultimately cancelled in June 2001 during its advanced development phase.

Development

The development focus centered on improving memory subsystem performance and enhancing scalability in multiprocessor environments. This direction was influenced heavily by Richard L. Sites’ notable Microprocessor Report article titled "It's the Memory, Stupid!" Sites, who co-led the definition of the Alpha architecture, stressed that memory system design would be the predominant challenge shaping microprocessor development over the subsequent decade.

Description

The Alpha 21364 is essentially an enhanced Alpha 21264 incorporating a larger on-chip secondary cache of 1.75 MB, alongside dual integrated memory controllers and a built-in network controller.

Core

Derived from the EV68CB core variant of the Alpha 21264, the main modification involved increasing the victim buffer capacity four times to a total of 32 entries—divided equally between Dcache and Scache buffers. Apart from this adjustment, the core architecture remained consistent with that of EV68CB.

Scache

The unified secondary cache ("Scache") features a capacity of 1.75 MB with a 7-way set associative structure, utilizing a line size of 64 bytes and operating under a write-back policy. It is protected by SECDED ECC and connects to the cache controller via a 128-bit data path. The cache is fully pipelined, providing bandwidth up to 16 GB/s at a clock speed of 1.0 GHz.

The data access latency stands at 12 cycles—a relatively high value that was not further reduced since it would not yield performance gains. The core design anticipated operation with external caches exhibiting higher latency; therefore, reducing Scache latency offered no advantage. Instead, design efforts concentrated on minimizing power consumption within the Scache. The elevated latency facilitated tag lookups prior to activating cache banks, thereby avoiding unnecessary power usage.

The tag store comprises approximately 5.75 million transistors, while the data store contains around 108 million transistors.

Memory controller

The Alpha 21364 incorporates a pair of specialized memory controllers designed for PC800 RDRAM, running at two-thirds the CPU frequency (800 MHz when the CPU is at 1.2 GHz). These controllers keep all 128 memory pages open simultaneously to minimize latency and include unique fault-tolerant mechanisms.

Each controller oversees five RDRAM channels—four dedicated to main memory and one reserved for RAID-like redundancy. Operating at 400 MHz with double data rate transfers (800 MT/s), each 16-bit channel delivers 1.6 GB/s bandwidth, resulting in a combined throughput of 12.8 GB/s across the eight channels.

Cache coherence is ensured by integrated coherence engines employing a directory-based MESI protocol, with part of the directory stored in memory.

R-box

The R-box houses the network router that links the processor to others via four directional ports: North, South, East, and West. Every port features two unidirectional 39-bit links running at 800 MHz, where 32 bits carry data and 7 bits provide error-correcting code (ECC). Additionally, a fifth I/O port connects to an IO7 ASIC, which interfaces an AGP 4x channel alongside two PCI-X buses. This I/O port utilizes two unidirectional 32-bit links operating at 200 MHz, offering a peak data rate of 3.2 GB/s.

Supporting up to 127 processors, the Alpha 21364 employs two network topologies: shuffle and two-dimensional torus. The shuffle topology provides reduced latency through more direct routing but is limited to eight processors. In contrast, the 2D torus accommodates up to 128 processors. Within these multiprocessor configurations, each processor functions as a node with its own local memory under a non-uniform memory access (NUMA) model, allowing access to remote nodes’ memory and I/O with latency proportional to their distance.

Fault tolerance

For fault-tolerant operation, the Alpha 21364 supports lock-step processing, a feature inspired by Compaq’s initiative to transition Tandem’s Himalaya servers from MIPS architectures to Alpha. Nonetheless, these servers never adopted the Alpha 21364 due to Hewlett-Packard’s subsequent decision to discontinue Alpha in favor of Itanium processors.

Fabrication

The Alpha 21364 integrates approximately 152 million transistors on a die measuring 397 mm² (21.1 mm by 18.8 mm), manufactured by IBM using a seven-level copper CMOS process at a 0.18 μm technology node. It is housed in a flip-chip land grid array (LGA) package featuring 1,443 lands, operates at a core voltage of 1.65 V with an external interface voltage of 1.5 V, and has a maximum thermal design power of 155 W at a clock speed of 1.25 GHz.

Alpha 21364A

The Alpha 21364A—also known by its code name EV79 (previously EV78)—represented an enhanced iteration of the Alpha 21364 and was intended as the final microprocessor in the Alpha series. Although planned for release in 2004, it was cancelled on October 23, 2003, due to difficulties meeting performance targets and schedule constraints; Hewlett-Packard instead introduced the EV7z as its successor.

A prototype showcased at the International Solid-State Circuits Conference in February 2003 ran at 1.45 GHz on a die measuring 251 mm², powered by a reduced voltage of 1.2 V with an estimated power dissipation around 100 W.

The design goals for the Alpha 21364A included achieving clock frequencies near 1.6–1.7 GHz and support for faster RDRAM running at 1066 Mbit/s. IBM was set to manufacture it utilizing an advanced silicon-on-insulator (SOI) process at the 0.13 μm scale, which would enable smaller die size, lower supply voltage (1.2 V compared to the previous 1.65 V), and reductions in both power consumption and thermal dissipation.

EV7z

The EV7z represented the last generation of the Alpha microprocessor series, derived from the Alpha 21364 architecture. Initially revealed on 23 October 2003, HP chose to discontinue the Alpha 21364A project in favor of developing the EV7z. This processor debuted on 16 August 2004, paired exclusively with the AlphaServer GS1280, which was the only platform to incorporate this chip. The EV7z and GS1280 were both phased out on 27 April 2007. Operating at a clock speed of 1.3 GHz, the EV7z supported PC1066 RIMMs and utilized the same 0.18 μm fabrication technology as its predecessor. While it delivered a performance boost of approximately 14–16% compared to the Alpha 21364, it fell short of the anticipated 25% improvement expected from the cancelled Alpha 21364A running at 1.5 GHz.