Alpha 21264

Digital Equipment Corporation
Company type	Public
Industry	Computer hardware, Microprocessors
Founded	November 8, 1957; 69 years ago in Massachusetts, United States
Fate	Acquired by Compaq (1998)
Headquarters	Maynard, Massachusetts, United States
Products	Alpha 21264 microprocessor

The Alpha 21264, also known by its codename EV6, is a RISC microprocessor created by Digital Equipment Corporation and introduced on October 19, 1998. It implements the Alpha instruction set architecture (ISA).

Description

The Alpha 21264 is a superscalar microprocessor capable of issuing four instructions per cycle, incorporating both out-of-order execution and speculative execution. It can reach a maximum throughput of six instructions per cycle and typically sustains four instructions per cycle, utilizing a seven-stage instruction pipeline.

Out of order execution

This processor can simultaneously handle up to 80 instructions at different stages of execution, a figure that surpasses many contemporaneous processors. Instructions that have been decoded are placed into queues and dispatched once their operands become available. The integer queue accommodates 20 entries, while the floating-point queue holds 15. Instructions are issued from these queues to match the availability of execution pipelines.

Ebox

The Ebox is responsible for processing integer, load, and store instructions, equipped with two integer units, two load/store units, and two integer register files. Each register file contains 80 entries: 32 architectural registers, 40 rename registers, and 8 PAL shadow registers. Following the Alpha architecture, register R31 is fixed at zero.

Each register file supports one integer unit and one load/store unit, forming two clusters labeled U0 and U1. This structure reduces the number of read/write ports needed, which decreases the size of the register files and allows for higher clock speeds. Synchronizing writes across the two register files takes one clock cycle, causing a minor performance reduction of roughly one percent. However, this drawback is compensated by increased clock rates and instruction issue logic that prioritizes independent instructions to avoid synchronization delays.

Both clusters are largely similar; however, U1 incorporates a seven-cycle pipelined multiplier, whereas U0 includes a three-cycle pipeline dedicated to Motion Video Instructions (MVI), an Alpha SIMD extension designed for multimedia applications.

Load/store units compute virtual addresses and execute simple arithmetic or logic operations. The instruction issue logic leverages this functionality to optimize unit utilization.

In total, the Ebox contains four 64-bit adders, four logic units, two barrel shifters, byte-manipulation logic, and two sets of conditional branch logic divided between clusters U0 and U1.

Fbox

Floating-point instructions are executed within the Fbox through two separate pipelines alongside a floating-point register file. One pipeline manages most floating-point operations, while the other specializes in multiplication. The adder pipeline also includes non-pipelined divide and square root units. Latencies for these operations are as follows: additions and multiplications take 4 cycles each; double-precision divides require 16 cycles; double-precision square roots take 33 cycles. The floating-point register file comprises 72 entries: 32 architectural registers and 40 rename registers.

Cache

The Alpha 21264 employs a two-level cache hierarchy consisting of primary and secondary caches. Unlike its predecessor, the Alpha 21164, it does not include an L3 ("victim") cache due to limitations in bandwidth.

Primary caches

The primary caches utilize a modified Harvard architecture featuring separate instruction (I-cache) and data caches (D-cache), each sized at 64 KB. The data cache is dual-ported by transferring data on both edges of the clock signal, allowing any combination of reads or writes every cycle without duplicating the cache hardware. This design maximizes cache capacity while reducing transistor count, silicon area, and power consumption compared to the duplicated cache structure found in the Alpha 21164.

B-cache

The secondary cache, known as the B-cache, is an external memory cache ranging in size from 1 to 16 MB and is managed directly by the microprocessor. It utilizes synchronous static RAM (SSRAM) chips running at a fraction of the internal clock speed, typically between 133 and 333 MHz when the core operates at 500 MHz. Access to this cache is facilitated through a dedicated 128-bit bus that operates at the SSRAM frequency or doubles that rate when employing double data rate SSRAM technology. The B-cache employs a direct-mapped caching scheme.

Branch prediction

Branch prediction relies on a tournament-based algorithm created by Scott McFarling at Digital's Western Research Laboratory. Given that the minimum penalty for a branch misprediction is seven cycles—and averages around eleven cycles due to instruction cache delays and pipeline queuing—precise prediction is essential for performance.

This prediction mechanism incorporates two history tables: a Local predictor and a Global predictor. A Choice predictor determines which of these two tables should be applied for each branch instruction.

- The local predictor consists of a two-level structure featuring a 1,024-entry history table with 10-bit entries and an associated 1,024-entry prediction table utilizing 3-bit saturating counters. - The global predictor uses a single-level table with 4,096 entries, each employing 2-bit saturating counters. - The choice predictor itself is a 4,096-entry table with 2-bit counters that decide whether to rely on the local or global predictor for individual branches.

External interface

The external interface includes a bidirectional 64-bit double data rate (DDR) data bus alongside two separate 15-bit unidirectional buses for time-multiplexed address and control signals—one set originating from the Alpha 21264 and the other from the system. Digital licensed this bus design to Advanced Micro Devices (AMD), who implemented it as the EV6 bus in their Athlon processors.

Memory addressing

The Alpha 21264 supports configurable virtual address widths of either 48 bits or 43 bits (equivalent to virtual address spaces of 256 TiB or 8 TiB), selectable via Internal Processor Register (IPR) control. Physical addresses can extend up to 44 bits, allowing access to as much as 16 TiB of physical memory. These capabilities represent an enhancement over earlier Alpha processors, which had more limited virtual and physical addressing ranges.

Fabrication

The Alpha 21264 chip contains approximately 15.2 million transistors—around six million dedicated to logic circuits, with the remainder allocated to caches and branch history tracking structures. The die measures 16.7 mm by 18.8 mm (totaling about 313.96 mm²) and was manufactured using a 0.35 micron CMOS process that features six layers of metal interconnects.

Packaging

This microprocessor was housed in a ceramic interstitial pin grid array (IPGA) package with 587 pins. Additionally, Alpha Processor, Inc. marketed it in a Slot B format, which mounted the CPU on a printed circuit board including the B-cache and voltage regulation components. This packaging approach aimed to capitalize on the market success of slot-based processors from Intel and AMD. Slot B was originally designed to support AMD’s Athlon processor line by enabling commodity pricing for components, thereby reducing costs for the Alpha 21264 and broadening its market penetration. However, since AMD ultimately chose Slot A for Athlon processors, this strategy was not realized.

Alpha 21264A

The Alpha 21264A, also known by its codename EV67, was introduced in late 1999 as a die-shrunk version running at clock speeds between 600 and 833 MHz. It marked the first Alpha processor to include the count extension (CIX), which added instructions for population count operations. Manufactured by Samsung Electronics using a 0.25 micron CMOS process combined with metal layers at 0.35 microns, the EV67 die measured approximately 210 mm². It operated at a voltage of 2.0 V and exhibited power dissipation ranging from 73 W at 600 MHz up to 90 W at 750 MHz.

Alpha 21264B

The Alpha 21264B represented an evolution of the Alpha 21264 series, achieving enhanced clock speeds. It was available in two versions: IBM's EV68C and Samsung's EV68A.

Samsung's EV68A utilized a 0.18 μm CMOS fabrication process with aluminium interconnects. The chip measured 125 mm², which was approximately one-third smaller than the preceding 21264A die, and operated at a voltage of 1.7 V. Introduced in 2001, it supported clock rates of 750, 833, 875, and 940 MHz, with power consumption ranging between 60 W and 75 W depending on the frequency.

IBM's EV68C variant employed a 0.18 μm CMOS process featuring copper interconnects. Sampled in early 2000, this version reached clock speeds up to 1.25 GHz.

In September 1998, Samsung announced plans for a 0.18 μm SOI version with copper interconnects targeting a frequency of 1.5 GHz; however, this model did not progress to production.

Alpha 21264C

The Alpha 21264C (also known as EV68CB) was offered at clock frequencies of 1.0, 1.25, and 1.33 GHz. Manufactured by IBM using a 0.18 μm CMOS process incorporating seven layers of copper interconnects and low-K dielectric material, the chip contained approximately 15.5 million transistors on a die area of 120 mm². It was housed in a flip-chip ceramic land grid array (CLGA) package with 675 pads and operated at a voltage of 1.7 V. Power dissipation varied from 64 W to 80 W depending on the operating frequency.

Alpha 21264D

The Alpha 21264D (EV68CD) represented a higher-performance IBM-produced iteration within the Alpha 21264 lineup.

Alpha 21264E

Samsung developed the Alpha 21264E (EV68E), which was announced in October 2000 for an anticipated mid-2001 release but ultimately cancelled prior to launch. This variant aimed to achieve a clock speed of 1.25 GHz and incorporate an on-chip secondary cache of 1.85 MB, fabricated using a 0.18 μm CMOS process with copper interconnect technology.

Chipsets

Key chipset solutions supporting the Alpha 21264 processor were developed by Digital and Advanced Micro Devices (AMD).

21272/21274

Digital produced the 21272 ("Tsunami") and 21274 ("Typhoon") chipsets as the initial platforms designed specifically for the Alpha 21264 CPU family. The simpler 21272 chipset supported one- or two-processor configurations and accommodated up to 8GB of memory, while the more advanced 21274 enabled multiprocessing with up to four CPUs and memory capacities reaching as high as 64GB. Both chipsets offered one or two PCI buses operating at 64-bit width and 33 MHz speed, alongside an 83 MHz memory bus delivering bandwidth up to 5,312 MB/s, compatible with registered ECC SDRAM modules.

Each chipset consisted of several components: the C-chip acting as the memory controller, the P-chip managing PCI control, and the D-chip responsible for DRAM operations. System configurations varied depending on requirements—for each CPU there was one C-chip, one or two P-chips for PCI management, and multiple D-chips handling memory access—ranging from two to four D-chips for the 21272 and two to eight for the more scalable 21274 model.

These chipsets were implemented in Digital, Compaq, and Hewlett Packard’s entry-level to mid-range AlphaServer models as well as all AlphaStation systems, in addition to third-party hardware such as API NetWorks’ UP2000+ motherboard platform.

Irongate

AMD created two chipset families compatible with the Alpha 21264 processor: the Irongate (AMD-751) and its follow-up Irongate-2 (AMD-761). Originally designed for Athlon processors, these chipsets utilized AMD’s licensed EV6 bus technology from Digital, ensuring compatibility in bus protocols between Athlon and Alpha processors. Samsung incorporated Irongate into their UP1000 and UP1100 motherboards, while Irongate-2 was deployed in their UP1500 system model.

References

Compaq Computer Corporation (July 1999). Alpha 21264 Microprocessor Hardware Reference Manual.
Compaq Computer Corporation (June 2001). 21264/EV68CB and 21264/EV68DC Hardware Reference Manual.
Compaq Computer Corporation (March 2002). 21264/EV67 Microprocessor Hardware Reference Manual.
Compaq Computer Corporation (March 2002). 21264/EV68A Microprocessor Hardware Reference Manual.
Gronowski, Paul E. et al. (1998). "High Performance Microprocessor Design". IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, pp. 676–686.
Gwennap, Linley (28 October 1996). "Digital 21264 Sets New Standard". Microprocessor Report, Vol. 10, No. 14.
Kessler, R. E.; McLellan, E. J.; Webb, D. A. (1998). "The Alpha 21264 Microprocessor Architecture". Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors. pp. 90–95.
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