Burroughs B1700
| Company type | Mainframe computer series |
|---|---|
| Industry | Computer hardware |
| Founded | January 1, 1970 |
| Headquarters | Santa Barbara, California; Liège, Belgium , United States; Belgium |
| Products | B1700, B1800, B1900 mainframe computers |
| Parent | Burroughs Corporation |
The Burroughs B1000 Series comprised a range of mainframe computers created by Burroughs Corporation during the 1970s, with software maintenance extending until 1987. This series consisted of three primary generations: the B1700, B1800, and B1900 models. Referred to as Burroughs Small Systems, these machines were positioned distinctly from the company's Burroughs Large Systems (B5000–B8000) and Burroughs Medium Systems (B2000–B4000) product lines.
Development of the B1700, initially known under the codename PLP ("Proper Language Processor"), was conducted at Burroughs' facility in Pasadena. Manufacturing commenced in the mid-1970s at plants located in Santa Barbara and Liège, Belgium, with the majority of design efforts based in Santa Barbara except for the B1830 model, which was engineered in Liège.
Writable control store
A defining feature of the B1000 series was its writable control store, which allowed it to simulate different computing architectures by loading various interpreters within the framework of the Burroughs MCP (Master Control Program). This capability enabled the system to run multiple programming languages such as COBOL and Fortran through separate virtual machines.
To bridge the "semantic gap" between high-level programming languages and hardware execution, Burroughs implemented a language-directed design philosophy that closely aligned hardware functionality with language requirements. While their large systems were optimized for ALGOL using stack-based architectures and medium systems focused on business-oriented languages like COBOL with Binary-coded decimal (BCD), the B1000 series adopted a more flexible strategy by employing idealized virtual machines adaptable to any programming language.
The hardware incorporated features that supported this adaptability, including bit-addressable memory, a variable-length arithmetic logic unit (ALU), and instruction decoding enhancements such as bitwise OR operations applied to the instruction register. Uniquely, the machine language treated ALU outputs as addressable registers, with specific read-only registers representing computations like X+Y and X−Y.
Internals
Designed primarily for business applications running COBOL, Burroughs systems integrated BCD arithmetic directly within the ALU.
The architecture utilized 16-bit instruction formats alongside a 24-bit data path, supported efficiently by bit-addressable memory. Subsequent memory designs stored data aligned on 32-bit boundaries but retained the ability to read across these boundaries to provide combined results.
Initial hardware implementations employed the Complementary Transistor Logic (CTL) family from Fairchild Semiconductor, transitioning later to the more widely used TTL technology with the release of the 1979 B1955 model. Up until this model, control logic was realized through a combination of PROMs and multiplexers.
The concluding B1965 model introduced dual microcode sequencers functioning synchronously. Most instructions were executed within a single cycle, initially decoded by FPLAs featuring 16 inputs—optimized for 16-bit instructions—and 48 min-terms. Instructions requiring multiple cycles utilized PROMs for sequential processing stages. Outputs from FPLAs and PROMs were integrated such that FPLAs first managed control signals, followed by PROMs completing instruction execution.
I/O
The input/output system of the B1000 series utilized a 24-bit data bus accompanied by control strobes to coordinate peripheral devices. The central processing units transmitted data onto the bus and managed adapter state machines through sequential accesses, illustrating the straightforward design typical of many peripheral adapters.
Subsequent models in the 1800 and 1900 series offered configurations with either one or two processors, featuring closely integrated memory access. The B1955 and B1965 models supported up to four processors connected via the memory bus; however, one processor was dedicated exclusively to the Multi-Line adapter responsible for serial input/output. Despite this capability, only dual-processor configurations were commercially available.
The Multi-Line adapter handled multiple RS485 serial lines operating at 19.2 Kb in a multi-drop arrangement, utilizing polled serial I/O. Terminals awaited their specific addressing before initiating data transmission.
Data transfers into main memory were conducted using direct memory access (DMA) with a linked list structure, thereby minimizing processor interruptions caused by serial I/O. This architecture was designed exclusively for block mode terminals.
Memory addressing in the B1000 series extended up to 2 megabytes—modest compared to modern standards but ample for most commercial uses that typically required storage measured in hundreds of kilobytes.
Notes
References
- B1700/B1800/B1900 manuals at bitsavers.org
- 1965 Mainframe Computers Employ ICS, article at www.computerhistory.org
- Barton, R. S., “Ideas for Computer Systems Organization: A Personal Survey”, Software Engineering, vol. 1, Academic Press, New York, 1970, pp.7-16.
- Wilner, Wayne T., "B1700 Design and Implementation", Burroughs Corporation, Santa Barbara Plant, May 1972.
- Wilner, Wayne T., "Microprogramming environment on the Burroughs B1700", IEEE CompCon '72
- Wilner, Wayne T., "Design of the Burroughs B1700", AFIPS Joint Computer Conferences Proceedings, December 1972, Anaheim, California, pp.489-497
- Wilner, Wayne T., "Burroughs B1700 memory utilization", Proceedings of the December 5-7, 1972 Fall Joint Computer Conference
- Wilner, Wayne T., "Unconventional architecture", ACM Annual Conference Proceedings, 1976, Houston, Texas