Cell (processor)

STI (Sony, Toshiba, IBM)
Company type	Consortium
Industry	Semiconductor, Microprocessor design
Founded	2001
Headquarters	Austin, United States
Products	Cell Broadband Engine (Cell/B.E.) microprocessor

The Cell Broadband Engine (Cell/B.E.) is a 64-bit reduced instruction set computer (RISC) multi-core processor created through a collaboration between Sony, Toshiba, and IBM, collectively known as "STI". It combines a versatile PowerPC core, the Power Processing Element (PPE), with several specialized coprocessors called Synergistic Processing Elements (SPEs), which are optimized for enhancing multimedia and vector processing operations.

The development of Cell spanned approximately four years starting in 2001, with Sony disclosing an investment near . Its initial prominent application appeared in Sony's PlayStation 3 console, released in 2006. A customized version of the Cell processor powered IBM's Roadrunner in 2008, marking the first supercomputer to achieve sustained performance of one petaFLOPS. Additional uses include high-performance computing platforms from Mercury Computer Systems and dedicated arcade system hardware.

Designed with an emphasis on memory coherence, energy efficiency, and maximum computational throughput, the Cell architecture posed considerable software development hurdles. To assist programmers, IBM provided a Linux-based software development kit tailored for this platform.

History

In mid-2000, Sony, Toshiba, and IBM established the STI alliance to engineer a novel microprocessor. The STI Design Center was inaugurated in March 2001 in Austin, Texas, engaging over 400 engineers across IBM’s eleven design facilities.

Early patent filings outlined a design featuring four Power Processing Elements (PPEs), each paired with eight Synergistic Processing Elements (SPEs), aiming for a 1 teraFLOPS target. Ultimately, only a streamlined version—one PPE combined with eight SPEs—was manufactured.

Production commenced using a 90 nm SOI (silicon on insulator) fabrication method. In March 2007, IBM transitioned to a 65 nm process, followed by adoption of a 45 nm process in February 2008. The Cell processor was also implemented by Bandai Namco Entertainment in its Namco System 357 and 369 arcade platforms.

IBM launched the PowerXCell 8i in May 2008, a double-precision variant incorporated into systems such as the Roadrunner supercomputer—the first to surpass one petaFLOPS sustained performance and holding the speed record until late 2009.

Although IBM discontinued development on higher-core-count Cell models (including a proposed 32-APU version) by late 2009, it maintained support for existing Cell-based products.

Commercialization

On May 17, 2005, Sony revealed the finalized Cell configuration for the PlayStation 3: featuring one PPE alongside seven active SPEs. To enhance production yields, chips are manufactured with eight SPEs; any defective SPE is disabled through laser trimming to reduce waste. Even flawless chips have one SPE deactivated to maintain consistency. Of the seven functional SPEs, six are accessible to developers while one is reserved exclusively for the console’s operating system. The processor operates at a clock speed of 3.2 GHz. Additionally, Sony utilized the Cell processor within its Zego high-performance media computing server.

The PPE supports simultaneous multithreading (SMT) with two threads per core, and each active SPE runs a single thread, enabling up to nine concurrent threads within the PlayStation 3 setup.

On June 28, 2005, IBM teamed with Mercury Computer Systems to integrate Cell processors into embedded systems targeting medical imaging, aerospace applications, and seismic data processing. Mercury employed the full Cell configuration with eight active SPEs and subsequently introduced blade servers and PCI Express accelerator cards based on this architecture.

In 2006, IBM released the QS20 blade server capable of delivering up to 410 gigaFLOPS in single-precision performance per module. The QS22 blade server variant utilizing the PowerXCell 8i was incorporated into IBM’s Roadrunner supercomputer. On April 8, 2008, Fixstars Corporation launched a PCI Express accelerator card featuring the PowerXCell 8i processor.

Overview

The Cell Broadband Engine (Cell) is a microprocessor engineered as a fusion of traditional desktop CPUs—such as those from the Athlon 64 and Core 2 series—and specialized, high-performance processors like NVIDIA and ATI graphics processing units (GPUs). Its designation highlights its intended application in contemporary and forthcoming online distribution platforms, including high-definition display technologies, recording devices, and HDTV systems. Additionally, it is well-suited for digital imaging applications in medical and scientific fields, as well as for conducting physical simulations relevant to scientific research and structural engineering modeling. The PlayStation 3’s Cell processor incorporates 250 million transistors.

The architecture of the Cell processor is composed of four principal elements: external input/output interfaces; the main processing unit known as the Power Processing Element (PPE)—a two-way simultaneous multithreaded PowerPC 2.02 core; eight auxiliary co-processors called Synergistic Processing Elements (SPEs); and a high-speed circular data bus that interconnects these components, referred to as the Element Interconnect Bus (EIB).

To achieve elevated performance levels in applications such as decoding or encoding MPEG streams, 3D graphics processing, or performing Fourier analysis, the Cell integrates the PPE and SPEs through the EIB. This setup allows fully cache-coherent DMA interactions with main memory and external storage devices. Each of the nine processing units contains its own DMA engine, facilitating efficient overlap between data transfer and computation. Because SPEs have access only to their local scratchpad memory, they depend on DMA operations to move data between main memory and other SPEs. These DMA transfers can handle either single blocks up to 16KB or multiple blocks via lists. This focus on DMA-driven design maximizes asynchronous operation and concurrency within the chip.

The PPE operates standard operating systems and oversees SPE management by initiating, halting, interrupting, and scheduling their tasks. It can perform read/write operations on both main memory and the local memories of SPEs using conventional load/store instructions. SPEs themselves are not self-starting; they require initialization by the PPE before execution can commence. While most computational throughput comes from the SPEs, their limited local memory capacity combined with reliance on DMA introduces complexity for software developers striving to optimize performance, necessitating meticulous program tuning.

The PPE along with the bus infrastructure supports multiple modes of operation that offer varying degrees of memory protection, enabling selective safeguarding of memory regions from access by particular processes running on either the PPE or SPEs.

Both PPE and SPE units utilize a RISC instruction set architecture featuring fixed-length 32-bit instructions. The PPE is equipped with 64-bit general-purpose registers (GPR), 64-bit floating-point registers (FPR), and 128-bit Altivec vector registers. In contrast, SPEs contain 128-bit registers capable of handling scalar data types ranging from 8 to 64 bits or executing SIMD operations on integer and floating-point data formats. System memory addresses are represented as 64-bit values, whereas local store addresses within an SPU are specified in 32-bit words. For documentation purposes within Cell architecture, a word corresponds to 32 bits, a doubleword to 64 bits, and a quadword to 128 bits.

PowerXCell 8i

In 2008, IBM launched the PowerXCell 8i, an enhanced iteration of the Cell processor, incorporated into QS22 Blade Servers. Fabricated using a 65 nm technology, it accommodates up to 32 GB of DDR2 memory and markedly improves double-precision floating-point throughput on the SPEs—from roughly 12.8 GFLOPS to a total of 102.4 GFLOPS across eight SPEs, equating to the peak capabilities of the NEC SX-9 vector processor. The IBM Roadrunner supercomputer, which held the title of fastest worldwide in 2008–2009, employed 12,240 PowerXCell 8i processors alongside 6,562 AMD Opteron CPUs. Systems based on PowerXCell 8i also dominated the top six positions in the Green500 ranking for energy efficiency, recognized for their outstanding MFLOPS/Watt performance. Besides QS22 and supercomputing applications, the PowerXCell is offered as a PCI Express accelerator and is utilized as the main processor in the QPACE initiative.

The transition from RAMBUS to larger DDR2 memory and upgraded SPEs necessitated a redesign of the chip layout, resulting in an increased die size and modified packaging.

Architecture

The Cell processor employs a multi-core architecture consisting of a single "Power Processor Element" (PPE) coupled with multiple "Synergistic Processing Elements" (SPEs). These units communicate through a high-speed internal network known as the "Element Interconnect Bus" (EIB).

Power Processor Element (PPE)

The PPE is a PowerPC-based CPU core featuring dual-issue, in-order execution with two-way simultaneous multithreading and a 23-stage pipeline. It functions as the coordinator for eight SPEs responsible for most computational workloads. The PPE supports limited out-of-order execution primarily for load operations and incorporates delayed execution pipelines. Its architecture aligns with standard 64-bit PowerPC processors, enabling compatibility with conventional operating systems while delegating vectorized floating-point processing to the SPEs.

Cache memory within the PPE includes a 32 KiB L1 instruction cache, a 32 KiB L1 data cache, and a 512 KiB L2 cache, all organized with 128-byte cache lines. IBM integrated a fully pipelined AltiVec (VMX) unit optimized for single-precision floating-point calculations, alongside components such as a 32-bit Fixed Point Unit (FXU), Load and Store Unit (LSU), Floating-Point Unit (FPU), Branch Unit (BRU), and Branch Execution Unit (BXU).

The PPE’s structure comprises three primary units: the Instruction Unit (IU), which contains the L1 instruction cache and branch prediction logic; the Execution Unit (XU), responsible for integer operations and load-store tasks; and the Vector/Scalar Execution Unit (VSU), which houses FPU and VMX functionalities. Each PPE can execute two double-precision fused multiply-add operations per clock cycle (yielding 6.4 GFLOPS at 3.2 GHz) or eight single-precision fused multiply-add operations per cycle via vector instructions (achieving 25.6 GFLOPS at 3.2 GHz).

Xenon in Xbox 360

Based on the PPE originally developed for the Cell processor, IBM adapted this core at Microsoft's request to produce the tri-core Xenon processor used in the Xbox 360. This version incorporated VMX128 extensions into the PPE design, delivering enhanced performance tailored specifically for gaming workloads.

Synergistic Processing Element (SPE)

An SPE integrates a "Synergistic Processing Unit" (SPU) with a "Memory Flow Controller" (MFC), which manages DMA operations, memory management, and bus interfaces. Lacking branch prediction hardware, SPEs depend extensively on compiler-driven optimizations. The SPU executes a dedicated 128-bit SIMD instruction set that supports both single and double precision calculations.

Each SPE is equipped with 256 KB of embedded SRAM known as "Local Storage," which can be directly accessed by the PPE and supports addressing up to 4 GiB of local memory. Unlike traditional CPU caches, this local store requires explicit control by software. The SPE contains a 128-bit register file with 128 entries and occupies an area of 14.5 mm² using a 90 nm fabrication process. It is capable of processing sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, or four single-precision floating-point values simultaneously per clock cycle, alongside performing a memory operation. Access to system memory occurs indirectly through the MFC via DMA transfers.

Common applications involve loading small programs onto SPEs that perform sequential processing steps—such as in set-top boxes for DVD playback, decoding, and rendering—or executing parallel data processing tasks. Operating at 3.2 GHz, each SPE can deliver up to 25.6 GFLOPS in single-precision floating-point performance.

While the Cell processor's floating-point capabilities surpass those of contemporary CPUs like the Pentium 4 and Athlon 64, general-purpose desktop processors maintain an advantage in versatile workloads due to features such as branch prediction. Although double-precision performance on Cell processors is comparatively lower, it remains competitive; the PowerXCell 8i variant achieves up to 102.4 GFLOPS in double precision, targeting markets requiring scientific computation.

IBM's performance tests reveal that SPEs can reach approximately 98% of their theoretical maximum in optimized parallel matrix multiplication scenarios.

Toshiba created the SpursEngine, a co-processor containing four SPEs but lacking a PPE, designed specifically to accelerate three-dimensional graphics and video effects for consumer electronics.

Collectively, the six SPEs within a Cell processor provide 2 MB of local storage, which is essential for handling high-throughput data processing demands in multimedia and gaming contexts.

Element Interconnect Bus (EIB)

The EIB serves as the internal communication backbone of the Cell processor, connecting the PPE, memory interface controller (MIC), eight SPE coprocessors, and two external I/O interfaces—amounting to twelve participants in the PS3 configuration (with varying numbers of SPEs in other implementations). An arbitration mechanism governs traffic flow across the bus. IBM often refers to these connected components as 'units'.

Structurally, the EIB is implemented as a circular ring composed of four unidirectional channels, each 16 bytes wide, arranged in two pairs rotating in opposite directions. Each channel supports up to three simultaneous transactions. Operating at half the system clock frequency, each channel effectively transfers 16 bytes every two system clock cycles. At maximum concurrency—three transactions per channel on all four channels—the EIB can theoretically achieve a bandwidth of 96 bytes per clock cycle (calculated as 12 transactions × 16 bytes divided by 2 clocks). However, arbitration mechanisms impose practical limits on achievable throughput.

David Krolak, IBM's senior engineer responsible for EIB design, explains the concurrency model:

Every participant is assigned one read port and one write port, each capable of transferring 16 bytes per EIB clock cycle (commonly interpreted as 8 bytes per system clock). Each SPU includes a dedicated DMA queue that schedules extended transaction sequences without interrupting ongoing computations; these queues may be controlled locally or remotely to provide enhanced scheduling flexibility.

Data circulates incrementally around the ring among twelve participants; the maximum distance between any two units is six steps. If data must travel further than six steps in one direction, it takes the shorter path by moving counterclockwise around the ring. Although latency differences due to step count are minimal because of high clock speeds, longer distances reduce concurrency and overall throughput.

Initially considering a crossbar switch for interconnect design, IBM opted for the circular ring architecture due to spatial constraints on-chip. This design rarely restricts overall Cell processor performance but requires programmers to carefully plan communication patterns that preserve high concurrency levels.

David Krolak provided further insights:

Bandwidth Evaluation

Operating at 3.2 GHz, each channel provides a throughput of 25.6 GB/s, culminating in a theoretical EIB bandwidth of 307.2 GB/s when managing twelve simultaneous transactions. IBM literature frequently references the EIB bandwidth as exceeding 300 GB/s, indicating peak instantaneous throughput scaled by the processor's clock speed.

Nevertheless, arbitration constraints are in place. According to insights from the IBM Systems Performance team:

This marks the limit of IBM's publicly available information regarding arbitration and snooping protocols, which remain largely undisclosed.

The practical EIB bandwidth is further limited by connected system elements: every one of the nine cores can handle 25.6 GB/s for both reading and writing concurrently; the memory interface controller (MIC) connects to two XDR memory channels with an aggregate maximum throughput of 25.6 GB/s (read/write); and two I/O controllers support a combined peak input bandwidth of 25.6 GB/s and output bandwidth up to 35 GB/s.

Earlier documentation citing a 4 GHz clock speed reports higher instantaneous bandwidths (384 GB/s) but reduced arbitration-limited throughput (256 GB/s). Overall, the commonly accepted theoretical bandwidth is 204.8 GB/s, supported by SPU-centric data transfer rates reaching approximately 197 GB/s on a Cell processor running at 3.2 GHz.

Memory and I/O Controllers

The Cell processor incorporates a dual-channel Rambus XIO macro that interfaces with Rambus XDR memory through an IBM-engineered memory interface controller (MIC). The connection between XIO and XDR operates at 3.2 Gbit/s per pin; with two 32-bit channels, this yields a theoretical peak bandwidth of 25.6 GB/s.

The I/O subsystem employs Rambus-designed FlexIO technology, consisting of twelve unidirectional lanes—five inbound lanes (each 8 bits wide) and seven outbound lanes—offering a maximum theoretical bandwidth of 62.4 GB/s (36.4 GB/s outbound and 26 GB/s inbound) at a frequency of 2.6 GHz. FlexIO can function independently, generally running at 3.2 GHz, with four inbound and four outbound lanes supporting memory coherency.

Video Processing Card

Manufacturers such as Leadtek have developed PCI-E expansion cards utilizing the Cell processor to achieve transcoding speeds for H.264, MPEG-2, and MPEG-4 video formats that exceed real-time performance.

Blade Server

On August 29, 2007, IBM unveiled the BladeCenter QS21, delivering energy efficiency of approximately 1.05 gigaFLOPS per watt alongside peak computational power near 460 GFLOPS, positioning it as a highly power-efficient solution. A single BladeCenter chassis can achieve up to 6.4 teraFLOPS, scaling beyond 25.8 teraFLOPS within a standard 42U rack configuration.

IBM followed with the release of the BladeCenter QS22 on May 13, 2008, featuring the PowerXCell 8i processor which offered quintupled double-precision floating-point performance compared to the QS21 and supported up to 32 GB DDR2 memory on blade.

The Cell-based Blade server product line was officially discontinued by IBM on January 12, 2012.

PCI Express Board

Multiple vendors provide PCI-e boards equipped with the IBM PowerXCell 8i processor, capable of delivering performance figures of up to 179.2 GFlops in single precision and 89.6 GFlops in double precision when operating at 2.8 GHz.

Console Video Games

The first commercial deployment of the Cell processor was in Sony’s PlayStation 3, which operates at a clock rate of 3.2 GHz with seven out of eight SPEs enabled to enhance manufacturing yield. Of these SPEs, six are accessible to game developers while one remains reserved for operating system use.

Home theater systems

Toshiba introduced HDTV models incorporating Cell technology, demonstrating a platform capable of simultaneously decoding 48 MPEG-2 standard definition streams on a 1920×1080 resolution display. This advancement enables viewers to browse through numerous channel thumbnails displayed at once for easy selection.

Notebook computers

In 2008, Toshiba launched the Qosmio G55 laptop, which integrated Cell processors alongside a conventional Intel Core x86 CPU, combining cutting-edge processing power with established computing architecture.

High-performance computing

IBM's Roadrunner supercomputer, which integrated x86-64 Opteron and Cell processors, secured the leading position on the June 2008 Top 500 ranking. It was the first system to exceed petaflop performance, sustaining 1.026 petaflops on the LINPACK benchmark. The machine employed PowerXCell 8i processors manufactured with 65 nm technology, featuring enhanced SPUs capable of double precision operations at 102 GFLOPs per chip.

Cluster computing

Clusters composed of PlayStation 3 units provide an economical alternative to expensive Cell blade configurations. Research led by Jack Dongarra at the University of Tennessee's Innovative Computing Laboratory has extensively explored this approach. Based on Dongarra’s findings, Terrasoft Solutions offers PS3 clusters in 8-node and 32-node configurations preloaded with Yellow Dog Linux.

Astrophysicist Gaurav Khanna from University of Massachusetts Dartmouth substituted traditional supercomputer time with an eight-PS3 cluster in 2007 to simulate black hole phenomena. The subsequent iteration, the PlayStation 3 Gravity Grid, employs 16 PS3 consoles, exploiting the Cell processor’s design for modeling binary black hole mergers through perturbation theory. This setup performs astrophysical simulations of supermassive black holes capturing smaller bodies, generating data published in academic journals. Each PS3 includes one main CPU and six SPEs, resulting in a total of 16 general-purpose and 96 vector processors across the cluster, assembled at approximately $9,000—far less costly than the $6,000 per run typical on conventional supercomputers. Khanna notes that this configuration outperforms Linux clusters with over 100 Intel Xeon cores for his specific simulations. The Gravity Grid received media coverage from 2007 to 2010.

The Computational Biochemistry and Biophysics group at Universitat Pompeu Fabra, Barcelona, initiated the BOINC-based PS3GRID in 2007 to enable distributed computing using CellMD software optimized for Cell processors.

The United States Air Force Research Laboratory deployed a "Condor Cluster" composed of over 1,700 PlayStation 3 units to process high-resolution satellite imagery. This cluster ranks as the world’s 33rd largest supercomputer by capacity and has been made accessible to academic institutions for research purposes.

Distributed computing

The distributed computing initiative Folding@home harnesses the power of more than half a million PlayStation 3 consoles and holds the Guinness World Records distinction as the most powerful distributed network worldwide. On September 16, 2007, it surpassed one petaFLOPS, an unprecedented achievement for a distributed system. By September 23, 2007, PS3 consoles alone had reached this petaFLOPS threshold. For comparison, IBM’s Blue Gene/L supercomputer operated around 478.2 teraFLOPS at that time, meaning Folding@home’s computational capacity was roughly twice as large despite Blue Gene/L’s CPU interconnect being more than a million times faster than Folding@home’s average network speed. By May 7, 2011, Folding@home had attained approximately 9.3 x86 petaflops overall, with about 1.6 petaflops contributed by some 26,000 active PS3 units.

Mainframes

On April 25, 2007, IBM revealed plans to incorporate its Cell Broadband Engine Architecture microprocessors into the System z mainframe series. This development gave rise to the gameframe, a hybrid system merging gaming technology with mainframe performance.

Password cracking

The architecture of the Cell processor is notably advantageous for hardware-accelerated cryptographic brute-force attack operations, delivering superior performance compared to standard processors in password recovery tasks.

Software engineering

The Cell’s adaptable design accommodates diverse computing models and resource management strategies beyond conventional frameworks:

Job queue

The PPE oversees a job queue by allocating tasks to SPEs and tracking their progress. Each SPE operates a "mini kernel" responsible for retrieving jobs, carrying them out, and coordinating with the PPE.

Self-multitasking of SPEs

Scheduling within the mini kernels is decentralized among SPEs. Synchronization of tasks occurs through mutexes or semaphores, paralleling typical operating system process management. Tasks that are ready wait in a queue for execution on SPEs via shared memory.

Stream processing

Each SPE executes an independent program, handling data from input streams and producing output streams. This configuration facilitates robust and flexible stream processing with explicit control over scheduling per SPE. While other processors can perform streaming tasks, they are restricted by their kernel environments.

Open source software development

In 2005, IBM engineers contributed patches to integrate Cell support into the Linux kernel. Official Linux compatibility with the Cell processor was established by version 2.6.16 in March 2006. Both PPE and SPEs can be programmed in C/C++ through a unified API.

Fixstars Solutions provides Yellow Dog Linux tailored for IBM and Mercury Cell platforms, including the PlayStation 3. Collaborating with Mercury, Terra Soft delivers a Linux Board Support Package for Cell-based systems such as IBM BladeCenter JS21 and Cell QS20, facilitating software development across these architectures. Additionally, Terra Soft maintains the Y-HPC Cluster Management Suite and Y-Bio gene sequencing applications, thereby advancing bioinformatics research capabilities.

IBM created "Spufs," a pseudo-filesystem designed to streamline access to SPE resources on Linux systems. IBM also sustains Linux kernel and GDB ports, while Sony is responsible for maintaining the GNU toolchain components (GCC, binutils).

In November 2005, IBM introduced the "Cell Broadband Engine (CBE) Software Development Kit Version 1.0," which included simulation tools and development utilities. The Barcelona Supercomputing Center manages ongoing development versions of kernels and tools for Fedora Core 4. Mercury Computer Systems released a Software Development Kit in August 2007 for PlayStation 3 aimed at high-performance computing applications.

Fixstars launched "CVCell" in November 2007, a module that accelerates critical OpenCV APIs on Cell processors, achieving performance improvements ranging from 6 to 27 times faster than a 2.4 GHz Intel Core 2 Duo when running on a 3.2 GHz Cell processor.

In October 2009, IBM rolled out an OpenCL driver compatible with POWER6 and CBE architectures, enabling efficient execution of cross-platform API programs on Cell PSE hardware.

Gallery

Depictions showcasing different iterations of the Cell/B.E. processors alongside the PowerXCell 8i. Each Cell/B.E. module measures 42.5×42.5 mm, whereas the PowerXCell 8i is slightly larger at 47.5×47.5 mm.

External links