Power Processing Element
| Company type | Microprocessor core |
|---|---|
| Industry | Semiconductor, Computing |
| Products | 64-bit dual-threaded PowerPC 2.02 microprocessor core |
The Power Processing Element (PPE) comprises a Power Processing Unit (PPU) alongside a 512 KB L2 cache. The PPU is a 64-bit dual-threaded, in-order PowerPC 2.02 microprocessor core developed by IBM, primarily intended for gaming systems such as the PlayStation 3 and Xbox 360. Additionally, it is utilized in high-performance computing environments, including the supercomputer IBM Roadrunner.
This PPU acts as the central CPU core within three distinct processor architectures:
- The Cell Broadband Engine (Cell BE), predominantly found in Sony’s PlayStation 3, produced in 90 nm, 65 nm, and 45 nm fabrication processes.
- The PowerXCell 8i, a refined version of the Cell BE with enhancements to the floating-point unit and memory subsystem, manufactured exclusively using a 65 nm process.
- The XCPU, which integrates three cores and a unified 1 MB L2 cache within Microsoft’s Xbox 360, available in 90 nm, 65 nm, and a 45 nm XCGPU variant that incorporates an ATI graphics processor.
Core specifications
- Dual-threaded, 64-bit core
- Operating frequency typically at 3.2 GHz
- 32 KB L1 cache for instructions
- 32 KB L1 cache for data
- Unified 512 KB L2 cache with an 8-way set associative design in the PPE model
- Adheres to PowerPC ISA version 2.02 (POWER4 and PowerPC 970)
- Supports AltiVec SIMD instruction set
Functional units
- Branch Unit (BRU)
- Fixed Point Integer Unit (FXU)
- Load and Store Unit (LSU)
- Floating-Point Unit (FPU)
- Vector Media Extension Unit (VMX)
In-order execution
The PPU employs an in-order execution model but incorporates mechanisms that emulate certain advantages of out-of-order execution without the complexity of reorder buffers. Upon an L1 cache miss, it continues processing subsequent instructions until it reaches one dependent on the missing data. It can issue up to eight load instructions to the L2 cache out-of-order. A specialized instruction delay pipeline permits execution of instructions that would typically cause pipeline stalls without interrupting the main pipeline flow by handling Out-Of-Order Load/Store operations through deferring cache misses.
Pipeline architecture
The PPE utilizes a general pipeline consisting of 23 stages, supplemented by up to 11 microcode stages and four stages dedicated to branch prediction.
Simultaneous multithreading
This PPU supports two hardware threads running concurrently, replicating primary registers, exception and interrupt registers, as well as critical queues. Each thread independently manages exceptions and branch prediction. Despite this multithreading capability, execution units and caches are shared, maintaining a single-core configuration.
Floating-point performance
Equipped with a 64-bit double-precision FPU and a 128-bit VMX unit based on AltiVec technology, the PPU can execute up to twelve floating-point operations per cycle—combining multiply-add instructions at no less than 64 bits—resulting in a throughput of approximately 38.4 billion floating-point operations per second at a clock speed of 3.2 GHz.
Within the PowerXCell 8i processor, the PPU has been optimized for single-cycle double-precision floating-point operations to meet the demands of high-performance computing tasks typical in supercomputers.
For the Xbox 360’s XCPU, its VMX unit includes 128 registers and exhibits differences from standard AltiVec implementation.