CoreConnect
| Company type | Bus architecture |
|---|---|
| Industry | Semiconductor, Embedded systems |
| Founder | IBM |
Area served | Global |
| Products | Processor Local Bus (PLB), On-chip Peripheral Bus (OPB), Device Control Register (DCR) bus |
| Owner | IBM |
CoreConnect represents an IBM microprocessor bus architecture tailored for system-on-a-chip (SoC) implementations, promoting the seamless integration and reuse of processor, system, and peripheral core components. It functions as a foundational SoC design standard for both IBM and external vendors. The architecture comprises several vital elements: the processor local bus (PLB), on-chip peripheral bus (OPB), a bridging bus, and the device control register (DCR) bus. High-speed peripherals interface through the PLB, which offers substantial bandwidth and minimal latency, whereas lower-speed peripherals connect via the OPB to alleviate PLB congestion. Additionally, CoreConnect provides interoperability with the competing AMBA standard, facilitating the reuse of pre-existing SoC modules.
IBM offers CoreConnect licenses without royalty fees to tool manufacturers, IP providers, and semiconductor developers. This architecture is adopted by over 1500 companies in the electronics sector, including major players like Cadence, Ericsson, Lucent, Nokia, Siemens, and Synopsys.
Serving as a cornerstone in IBM’s embedded systems portfolio, CoreConnect is extensively utilized within their PowerPC 4x0 product lines. Historically, Xilinx incorporated CoreConnect as the backbone for all their embedded processor frameworks.
Processor Local Bus (PLB)
- A general-purpose, synchronous bus without multiplexing
- Distinct read and write data pathways enabling simultaneous operations
- Features multimaster capability with programmable priority arbitration
- Supports addressing from 32 to 64 bits; data widths of 32, 64, or 128 bits (expandable to 256 bits)
- Operates at frequencies of 66, 133, or 183 MHz depending on configuration
- Implements pipelining with early split transactions and overlapping arbitration phases
- Accommodates fixed or variable burst lengths along with bus locking mechanisms
- Delivers high throughput up to 2.9 GB/s
On-chip Peripheral Bus (OPB)
- Optimized for connecting slower peripheral devices
- Synchronous, nonmultiplexed multimaster bus featuring arbitration
- Supports addressing up to 64 bits; separate 32-bit read and write buses
- Employs pipelined transactions combined with overlapped arbitration
- Enables burst transfers and dynamic bus sizing supporting 8-, 16-, and 32-bit peripherals
- Provides single-cycle data transfers along with bus locking (parking) capabilities
Device Control Register (DCR) bus
- Synchronous bus with a single master and multiple slaves designed for CPU-to-slave general-purpose register data exchange
- Nonmultiplexed design featuring separate read and write buses
- Utilizes a 10-bit address bus alongside a 32-bit data bus
- Minimum two-cycle read/write operations facilitated by a distributed multiplexer architecture
- Compatible with 8-, 16-, and 32-bit devices supporting single-cycle data transfers