PowerPC 400

Applied Micro Circuits Corporation
Company type	Public
Industry	Semiconductors
Area served	Worldwide
Products	PowerPC 400 series processors

The PowerPC 400 series comprises 32-bit embedded RISC processor cores that implement the PowerPC or Power ISA instruction set architectures. These cores are tailored for niche applications such as system-on-a-chip (SoC) microcontrollers, network equipment, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), set-top boxes, storage solutions, and even supercomputer systems.

In April 2004, Applied Micro Circuits Corporation (AMCC) purchased the intellectual property related to the 400 family cores from IBM for $227 million and now distributes these processors under its own label. IBM remains involved in core development and continues to provide design and foundry services. Additionally, several cores are available for original equipment manufacturer (OEM) licensing through IBM and Synopsys.

Variants

Model	Pipeline Stages
PowerPC 401	3
PowerPC 405	5
PowerPC 440	7
PowerPC 470	9

PowerPC 403

Launched in 1994, the PowerPC 403 was one of the earliest PowerPC processors specifically developed for embedded systems. Unlike contemporaries such as the PowerPC 601, PowerPC 603, and PowerPC 604, it was positioned as a low-end processor, lacking both a memory management unit (MMU) and floating-point unit (FPU). It was available either as a core for custom chip integration or in packaged versions offering optional MMUs, with clock speeds ranging from 20 to 80 MHz.

The 403 core found applications in thin clients, set-top boxes, RAID controllers, network switches, and printers. A notable example is the initial TiVo device, which utilized a 54 MHz PowerPC 403GCX. After AMCC acquired the design in 2004, they opted not to continue marketing this core, instead concentrating on the 405 and 440 models.

PowerPC 401

Introduced by IBM in 1996 to serve cost-sensitive markets where the 403 was considered too complex or costly, the PowerPC 401 is a minimalist design featuring a single-issue, three-stage pipeline without MMU or DMA capabilities. It incorporates modest L1 caches—2 KB for instructions and 1 KB for data. With only about 85,000 transistors, it operates at frequencies up to 100 MHz while consuming less than 0.1 watts.

The PowerPC 401 core has been deployed in devices such as set-top boxes, telecommunications switches, printers, and fax machines.

PowerPC 405

Unveiled in 1998, the PowerPC 405 is aimed at low-end embedded SoC designs requiring a balance of cost-efficiency and performance. It features a five-stage pipeline architecture with separate L1 caches of 16 KB each for instructions and data, utilizes a CoreConnect bus, includes an Auxiliary Processing Unit (APU) interface, and supports clock speeds exceeding 400 MHz. This core adheres to the Power ISA v.2.03 Book III-E standard. Both AMCC and IBM continue to develop and market processors based on the 405 core, with IBM and Synopsys providing fully synthesizable versions. The specifications for the PowerPC 405 have also been made accessible to academic institutions and research organizations.

Typical applications encompass digital cameras, modems, set-top boxes—such as IBM's STB04xxx series—cell phones, GPS units, printers, fax machines, network interface cards, switches, storage devices, and server service processors. Up to two instances of the PowerPC 405 core are integrated within Xilinx Virtex-II Pro and Virtex-4 FPGA platforms. In addition, in 2004 Hifn acquired IBM’s PowerNP network processors that are based on this core.

: Some later slim versions of the PlayStation 2 employed a PowerPC 405 chip that emulated the MIPS R3000A I/O processor used in earlier models.

: The Chinese firm Culturecom utilizes a PowerPC 405 core within its V-Dragon processor designed for Linux-based terminals and set-top boxes. This processor integrates a Multilingual Character Generation Engine (MCGE), enabling direct handling of Chinese characters inside the CPU.

APM801xx: The APM801xx line of SoCs from AppliedMicro is built around the PowerPC 405 core and is recognized for its energy efficiency—operating up to approximately 800 MHz at around one watt power consumption or as low as 0.3 watts when idle. These processors serve diverse roles spanning networking equipment to storage and multimedia devices.

POWER8 on-chip controller: Within the POWER8 processor lies an embedded power and thermal management microcontroller known as the on-chip controller (OCC), which is based on the PowerPC 405 architecture and features dedicated SRAM of 512 KB to oversee chip operations.

PowerPC 440

Launched in 1999, IBM introduced the PowerPC 440 as its inaugural core implementing the Book E extension, incorporating CoreConnect bus technology to facilitate integration within PowerPC-based system-on-a-chip (SoC) designs.

This advanced core boasts separate 32 KB L1 caches for instructions and data, a seven-stage out-of-order dual-issue pipeline, clock speeds reaching up to 800 MHz, and optional L2 caches up to 256 KB. Although it does not include a built-in floating-point unit (FPU), it supports a four-stage FPU through the Auxiliary Processing Unit (APU) interface. The core adheres to the Power ISA v.2.03 Book III-E standard.

Xilinx incorporates one or two of these cores in its Virtex-5 FXT FPGA series. Both AMCC and IBM offer standalone processors based on the 440 core, while IBM and Synopsys provide fully synthesized implementations.

BRE440 Rad Hard SOC: Broad Reach Engineering created a radiation-hardened embedded SoC utilizing the IBM 440 synthesized core. This design includes Ethernet MACs, PCI, memory controllers, DMA, EDAC, SIO, along with 32 KB L1 cache and 256 KB L2 cache. Manufactured using Honeywell's HX5000 rad-hard process at 150 nm, it operates at frequencies up to 150 MHz.

QCDOC: The QCDOC supercomputer employs custom ASICs based on the 440 core, achieving peak computational performance near 10 TFLOPS for demanding quantum physics simulations.

Blue Gene/L: IBM’s Blue Gene/L supercomputer features processors with dual 440 cores each, delivering nearly 500 teraFLOPS peak performance and holding the top global supercomputing rank until June 2008.

SeaStar: PowerPC 440 cores drive SeaStar communication processors used in Cray XT3, XT4, and XT5 supercomputers. These processors enable high-speed inter-node data transfer through HyperTransport links, supporting bandwidths up to 9.6 GB/s with integrated error correction in the SeaStar2+ version.

AMCC 460: AMCC’s PowerPC 460EX and 460GT CPUs are derived from the 440 core architecture, operating between 0.6 and 1.2 GHz. They integrate DDR/DDR2 SDRAM controllers along with USB 2.0, PCIe, SATA interfaces, and Gigabit Ethernet connectivity.

Titan: Intrinsity developed the Titan core for AppliedMicro based on PowerPC 440 specifications. Intended for high-performance APM832xx SoCs, these products were ultimately not brought to market.

Virtex-5 FXT: Xilinx’s Virtex-5 FXT FPGA family embeds up to two PPC440 cores running at speeds up to 550 MHz. These cores connect via a crossbar switch that enhances system throughput by more than 2.6 times compared to earlier models.

LSI SAS: The PowerPC 440 core is integrated into multiple Serial Attached SCSI (SAS) controller chips by LSI, including the widely adopted SAS2008 model.

Acalis CPU872: CPU Tech’s Acalis CPU872 Security SoC targets critical mission applications such as military systems. Produced at IBM’s Trusted Foundry, it incorporates embedded DRAM, dual PowerPC 440 cores each with dual-precision FPUs, tamper-resistant features, and dedicated accelerators for secure communications and complex algorithm execution.

PowerPC 450

IBM designed and fabricated the processing core for the Blue Gene/P supercomputer closely related to the PowerPC 440 architecture, though detailed specifications remain limited.

Blue Gene/P: The Blue Gene/P processor integrates four PowerPC 450 cores running at 850 MHz, collectively delivering a total of 13.6 gigaflops. IBM emphasizes its energy-efficient design relative to other supercomputer processors.

PowerPC 460

Introduced in 2006, the 460 cores share similarities with the 440 series but operate at 1.4 GHz and enhance multi-core processing capabilities by incorporating 24 extra digital signal processing (DSP) instructions. Engineered for a balance of energy efficiency and robust performance, the 464-H90 core consumes merely 0.53 W at 1 GHz. This core adheres to the Power ISA v.2.03 specification as outlined in Book III-E.

The PowerPC 460S is a fully synthesizable core available for licensing from IBM or Synopsys and can be fabricated at various foundries. It features configurable L1 and L2 caches, with optional symmetric multiprocessing (SMP) and floating-point unit (FPU) support.
The PowerPC 464-H90, a hard macro fabricated on a 90 nm process and released in 2006, is intended as a customizable ASIC core produced by IBM, Chartered, or Samsung.
Released in 2007, the PowerPC 464FP-H90 extends the 464-H90 by integrating a double-precision floating-point unit (FPU).

AppliedMicro

The PowerPC 460SX and 460GTx processors, derived from the 464-H90 core, focus on high-performance storage and networking applications. They operate between 0.8 and 1.2 GHz and integrate a 512 KB L2 cache that doubles as SRAM, a DDR2 memory controller running at 400 MHz, four Gigabit Ethernet interfaces, PCIe controllers, and specialized accelerators tailored to specific applications. These chips are manufactured using a 90 nm technology node.
The APM82181 is a system-on-chip (SoC) based on the 464 core running from 0.8 to 1 GHz designed for storage solutions. It includes a DDR2 memory controller, a configurable 256 KB SRAM acting as L2 cache, PCIe, SATA2, USB2 ports, Gigabit Ethernet connectivity, alongside TCP/IP offload engines, RAID5 functionality, and cryptographic accelerators.
The APM86190 and APM86290 PACKETpro ("Mamba") are single- and dual-core SoCs built around the PowerPC 465 core clocked between 0.6 and 1.5 GHz. They feature separate instruction and data L1 caches of 32 KB each, a unified 256 KB L2 cache, DDR3 memory controller, PCIe interfaces, SATA2, USB2 support, Gigabit Ethernet ports, TCP/IP offloading capabilities, cryptography accelerators with secure boot mechanisms and tamper detection functions.
The APM86791 PACKETpro ("Keelback") is a single-core SoC utilizing the PowerPC 465 core at 1 GHz with cache sizes and peripheral interfaces comparable to those of "Mamba." It incorporates an ARM Cortex-M3 based cryptographic accelerator (SLIMpro) operating at 250 MHz that facilitates secure boot procedures and tampering detection.

PowerPC 470

The embedded and customizable PowerPC 470 core complies with Power ISA v2.05 Book III-E standards and was jointly developed by IBM and LSI Corporation. This core was implemented in the PowerPC 476FP introduced in 2009. The 476FP includes separate 32 KB instruction and data L1 caches, dual integer execution units, and a SIMD-capable double-precision floating-point unit supporting DSP instructions. Fabricated on a 45 nm process, it consumes approximately 1.6 W at a frequency of 1.6 GHz. Its pipeline features nine stages with out-of-order execution supporting five instructions per cycle; it can operate up to 2 GHz while interfacing with the PLB6 bus architecture. The design supports up to one megabyte of L2 cache and scales efficiently to SMP configurations with up to sixteen cores.

LSI’s Axxia ACP3448 integrates four PowerPC 476FP cores running at 1.8 GHz each, paired with dedicated 512 KB L2 caches per core and an on-chip shared L3 cache of four megabytes. It also includes dual DDR3 memory controllers, two 10 Gigabit Ethernet ports, three PCIe interfaces, plus network processing engines tailored for high-throughput applications.
The C*Core C1000 series consists of embedded processors based on the PowerPC 476FP core aimed at consumer electronics markets.
ChinaChip’s CC2000 combines a PowerPC 476FP core with integrated DSP and GPU components intended for use in gaming consoles.
The NTC Module’s NeuroMatrix model 1888TKh018 is an SoC designed specifically for onboard video processing and multimedia applications in aircraft systems.

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