Cray-1

Cray Research
Industry	Supercomputing
Founded	1972; 54 years ago
Founder	Seymour Cray, Lester Davis
Headquarters	United States
Products	Cray-1 supercomputer

The Cray-1 represented a groundbreaking supercomputer developed, produced, and distributed by Cray Research. Revealed in 1975, its inaugural installation occurred at Los Alamos National Laboratory in 1976. With sales reaching eighty units, it stands as one of the most commercially successful supercomputers ever created. Its unique C-shaped chassis housed a circular arrangement of benches that surrounded the power supply units and cooling apparatus.

As the first supercomputer to successfully utilize the vector processor architecture, the Cray-1 significantly improved mathematical computation speeds by structuring memory and registers to execute single instructions on extensive data arrays swiftly. Previous designs, such as the CDC STAR-100 and ASC, suffered from performance limitations caused by architectural shortcomings. The Cray-1 addressed these deficiencies, achieving processing rates multiple times faster than its contemporaries.

The project was spearheaded by architect Seymour Cray alongside chief engineer Lester Davis, a co-founder of Cray Research. Their pioneering work laid the groundwork for subsequent models that maintained top-tier performance throughout the 1990s.

History

Between 1968 and 1972, Seymour Cray at Control Data Corporation (CDC) worked on the CDC 8600, intended as the successor to the CDC 6600 and 7600 models. This system integrated four 7600 units and featured a specialized mode enabling lock-step SIMD execution. Simultaneously, Jim Thornton directed development of the more experimental CDC STAR-100, which prioritized hardware tailored for typical supercomputing operations over raw speed.

By 1972, progress on the 8600 was hindered by complexity and reliability challenges. Although Cray proposed a redesign to CDC CEO William Norris, budget limitations and ongoing commitment to the STAR project prevented further funding. As a result, Cray departed CDC and established Cray Research adjacent to CDC’s facility. Supported by investors connected through Wall Street networks, Cray Research concentrated on creating a novel supercomputer.

After four years of development, the Cray-1 running at 80 MHz was introduced in 1975. The strong demand led to competitive bids between Lawrence Livermore National Laboratory and Los Alamos National Laboratory, with Los Alamos acquiring serial number 001 in 1976 for evaluation purposes. The National Center for Atmospheric Research became the first official purchaser in 1977, obtaining serial number 3 for $8.86 million. Originally priced for a niche market, over eighty units sold at prices ranging from $5 million to $8 million each, securing Cray Research’s position as a supercomputing industry leader until the downturn of the early 1990s.

The National Security Agency (NSA), acting on William Perry’s advice, acquired a Cray-1 for cryptanalysis work, arguably making it the company’s earliest customer.

While the Cray-1 achieved 160 MFLOPS performance, it was eclipsed by the 1982 Cray X-MP delivering 800 MFLOPS with multiprocessing capabilities. The more advanced Cray-2 launched in 1985 reached a peak of 1.9 GFLOPS but experienced limited commercial adoption due to real-world performance issues. In response, the more conservative Cray Y-MP debuted in 1988 as an evolutionary follow-up.

For perspective, typical smart devices in 2013 operated near 1 GFLOPS,<ref> whereas Apple’s A13 chip powering the iPhone 11 in 2019 achieved approximately 154.9 GFLOPS,<ref> performance levels only matched by supercomputers released after the Cray-1 era around 1994.

Background

Scientific computing tasks often involve handling extensive data collections through uniform operations, such as incrementing each element in a data set containing millions of entries.

Traditional computing systems address this by iterating over every individual data item, resulting in the execution of millions of instructions. Each instruction encompasses several phases: fetching, decoding, retrieving operands, performing the operation, and storing the outcome, which collectively consume tens to hundreds of millions of clock cycles.

Vector machines

The STAR system introduced instructions that represented entire loops as single commands. Instead of issuing a million separate instructions, a single vector instruction like a(1..1000000) = addv b(1..1000000), c(1..1000000) was executed. While this reduced the number of instruction fetch and decode operations by roughly one million, the main benefit was realized internally within the processor.

A CPU is composed of dedicated functional units (such as those for addition or memory access) that traditionally execute tasks sequentially. Instruction pipelines allow overlapping these stages so that multiple instructions are processed simultaneously in a staged manner, enhancing throughput.

Vector processors take advantage of the predictable sequential layout of array data in memory. When a vector instruction is issued, specialized hardware optimizes memory access patterns and streams data efficiently into the processing units.

CDC’s STAR employed a memory-memory architecture, performing operations directly between memory locations rather than relying on register-based vectors. This design permitted flexible vector lengths but necessitated long pipelines to offset the latency of slow memory accesses. As a result, switching between vector and scalar modes involved significant overhead, and scalar processing performance was subpar. These drawbacks led to underwhelming practical results despite promising theoretical speedups, exemplifying constraints outlined by Amdahl's law.

Cray's approach

After examining the shortcomings of the STAR system, Cray determined that achieving high overall speed required not only rapid vector computation but also robust scalar performance to minimize penalties when switching modes. He also recognized that better utilization of registers could optimize workloads.

Unlike the STAR’s repeated memory reads during vector operations, Cray’s design loaded data once into CPU registers, allowing multiple computations per load and thus accelerating processing. However, registers were expensive in terms of hardware resources, limiting their quantity and consequently restricting vector length flexibility. Instead of processing entire vectors simultaneously, the Cray-1 handled portions sequentially but could perform multiple operations on each segment before writing results back to memory—a compromise Cray found appropriate for typical use cases.

The vector architecture included an independent pipeline; multiplication and addition units were implemented as separate hardware components supporting internal pipelining. This chaining capability allowed programmers to link instructions together for enhanced execution efficiency.

Performance

In 1978, Argonne National Laboratory evaluated several workloads on a Cray-1 as part of their initiative to replace their IBM 370/195. These tests took place on a Cray-1 at the National Center for Atmospheric Research (NCAR) in Boulder, Colorado, with limited access to other Cray systems.

Two testing conditions were documented: one involving minimal code modifications without vectorization and another with moderate changes enabling vectorization. The minimal conversion runs achieved performance on par with or up to twice that of the IBM 370, largely due to the Cray's extended exponent range. Implementing vectorization accelerated processing by factors ranging from 2.5 to 10 times. For instance, an internal fast Fourier transform completed in 3 milliseconds on the Cray-1 compared to 47 milliseconds on the IBM.

Description

The Cray-1 marked Cray's initial foray into utilizing integrated circuits (ICs), capitalizing on the performance improvements of early 1970s IC technology to achieve rapid computation speeds. This design incorporated only four distinct IC varieties: an ECL dual 5-4 NOR gate, a slower MECL 10K 5-4 NOR gate dedicated to address fanout, a 16×4-bit high-speed (6 ns) static RAM (SRAM) used for registers, and a 1,024×1-bit 48 ns SRAM serving as main memory. These components were procured from Fairchild Semiconductor and Motorola. Overall, the Cray-1 contained roughly 200,000 logic gates.

The ICs were installed on large five-layer printed circuit boards, each accommodating as many as 144 ICs. These boards were arranged in back-to-back pairs with copper plates between them to facilitate heat dissipation and mounted within twenty-four racks measuring 28 inches each, containing a total of 72 paired boards. The entire system consisted of 1,662 modules spanning 113 different types.

To maintain precise timing and minimize electrical interference, signal connections between modules utilized twisted-pair cables cut to exact lengths. The differential ECL signaling balanced the power load so effectively that the power supply operated without regulation, behaving essentially like a simple resistor within the system.

The ECL circuits' high-speed operation generated considerable heat, necessitating a sophisticated cooling mechanism. Each pair of boards was cooled by copper sheets linked to liquid Freon flowing through stainless steel tubing. Initial challenges with the cooling infrastructure caused a six-month delay in the first Cray-1's delivery, as improved welding methods were required to prevent lubricant leaks that led to electrical shorts.

For optimal speed, the chassis was curved into a substantial C-shape, positioning components critical to performance along the inner curve to reduce wiring lengths. This innovative layout facilitated a cycle time of 12.5 ns (equivalent to 80 MHz), surpassing contemporaries such as the CDC 7600 and STAR. According to NCAR estimates, its throughput was approximately 4.5 times greater than that of the CDC 7600.

The Cray-1 operated as a 64-bit machine with 24-bit addressing capability, supporting up to one megaword (1,048,576 words) of main memory plus eight parity bits per word for a total of 72 bits per word. Memory was divided into sixteen interleaved banks with a cycle time of 50 ns, enabling up to four words to be accessed per cycle. Smaller system configurations could be equipped with either 0.25 or 0.5 megawords of memory. The peak memory bandwidth reached 638 Mbit/s.

Its primary register file consisted of eight 64-bit scalar (S) registers alongside eight 24-bit address (A) registers, each supported by sixty-four temporary registers labeled T and B respectively. The vector processing unit included eight vector (V) registers sized at 64 elements by 64 bits each, as well as vector length and mask registers. Additional support came from a real-time clock register and four instruction buffers capable of holding sixty-four instructions of 16 bits each. Vector registers provided one word per clock cycle; scalar and address registers required two cycles; instruction buffers refilled over four cycles.

The Cray-1 incorporated twelve pipelined functional units: address arithmetic units for addition and multiplication; scalar units covering addition, logical operations, population count, leading zero count, and shifts; vector units for addition, logical operations, and shifts; plus shared floating-point units handling addition, multiplication, and reciprocal approximations.

Instruction-level parallelism was limited to issuing one instruction per clock cycle, yielding a theoretical peak performance of 80 MIPS; however, vector floating-point multiply and add operations could execute concurrently for up to 160 MFLOPS. The reciprocal approximation unit also operated in parallel but required multiple iterations for complete division calculations.

Input/output functionality was integrated via four six-channel controllers accessing main memory every four cycles. Each channel transmitted data at 16 bits wide with additional control and error-correction bits, achieving transfer rates up to one word every 100 ns—or roughly half a million words per second in aggregate throughput.

The original Cray-1A model weighed approximately , including its refrigeration system. With one million words of memory installed, it consumed about 115 kW of electrical power; combined cooling and storage systems likely doubled this consumption. Maintenance and control tasks such as booting were managed by a Data General SuperNova S/200 minicomputer acting as the maintenance control unit (MCU); subsequent models replaced this with the Data General Eclipse MCU.

By contemporary standards, reliability was modest; early adopters reported mean times between hardware failures around 96 hours in 1979. Seymour Cray prioritized computational speed over robustness in this initial design but addressed dependability improvements in later versions. The accompanying Cray Operating System (COS) began as a basic environment that underwent frequent enhancements during its early deployment phase.

Cray-1S

Unveiled in 1979, the Cray-1S represented an upgraded version of the Cray-1, offering expanded main memory capacities of 1, 2, or 4 million words. This enhancement was achieved through the use of 4,096 x 1-bit bipolar RAM integrated circuits with a 25 ns access speed. The earlier Data General minicomputers were optionally substituted by an internally developed 16-bit processor operating at 80 MIPS. The input/output subsystem was decoupled from the central unit and connected via a 6 Mbit/s control link alongside a 100 Mbit/s High Speed Data Channel, facilitating scalable I/O expansion. System configurations varied from the S/500 model, which lacked I/O and contained 0.5 million words of memory, up to the S/4400 featuring four I/O processors and 4 million words of memory.

Cray-1M

Launched in 1982 as the Cray-1S’s successor, the Cray-1M delivered a quicker 12 ns cycle time and incorporated more economical MOS RAM for its main memory. It was offered in three variants: the M/1200 with 1 million words distributed over eight banks, and the M/2200 and M/4200 models equipped with either 2 or 4 million words across sixteen banks. Each included between two and four I/O processors, with an option to add a second High Speed Data Channel. Additionally, users could expand storage with Solid-state Storage Devices containing from 8 to 32 million words of MOS RAM.

Software

The initial standardized software suite for the Cray-1 was introduced in 1978 and consisted of:

Cray Operating System (COS), later superseded by UNICOS, Cray’s UNIX-based system
Cray Assembly Language (CAL)
Cray FORTRAN (CFT), notable as the first Fortran compiler to automatically vectorize code

Prominent government research centers such as Lawrence Livermore, Los Alamos, Sandia National Laboratories, and NSF supercomputer facilities utilized specialized software including Lawrence Livermore’s Cray Time Sharing System (CTSS). CTSS originated from dynamic memory Fortran derivatives optimized for vector processing. Cray Research provided software support to these institutions, which influenced the development of subsequent minisupercomputers known as "crayettes."

Certain organizations developed their own operating systems: NCAR implemented NCAROS; the NSA created Folklore OS and the IMP programming language, alongside ports of Cray Pascal, C, and Fortran 90.

Early software libraries comprised those from Cray Research and Netlib. While alternative operating systems were available, Fortran-based languages remained predominant. Bell Laboratories ported the initial C compiler to the Cray-1—albeit without vectorization—enabling CRI’s early UNIX compatibility ahead of competitors like ETA Systems. This advancement supported projects such as Lucasfilm’s pioneering computer-generated animation The Adventures of André & Wally B..

The majority of application software was either classified—for example, nuclear simulations and cryptanalysis—or proprietary, such as petroleum reservoir modeling tools, restricting code sharing among clients and academic institutions. Exceptions were found in climatology and meteorology applications until NSF initiatives responded to Japan’s Fifth Generation Computer Systems project by establishing dedicated supercomputer centers.

To enhance visibility, Cray sponsored development of Cray Blitz, a chess program that secured major computer chess titles during the early 1980s, competing against programs previously dominant on Control Data Corporation supercomputers.

Museums

Cray-1 machines are displayed in numerous prominent museums globally, including:

Bradbury Science Museum located in Los Alamos, New Mexico
Chippewa Falls Museum of Industry and Technology in Chippewa Falls, Wisconsin
The headquarters of Cray Inc. at Cray Plaza, St. Paul, Minnesota
Computer History Museum situated in Mountain View, California
Mimms Museum of Technology and Art in Roswell, Georgia, housing four Cray-1 units along with other Cray models
DigiBarn Computer Museum
Deutsches Museum in Munich
ETH Zurich in Switzerland
Living Computers: Museum + Labs based in Seattle, Washington
National Center for Atmospheric Research located in Boulder, Colorado
National Air and Space Museum situated in Washington, D.C.
Musée Bolo in Lausanne, Switzerland
The National Museum of Computing at Bletchley Park
Science Museum (London) located in London
Swedish National Museum of Science and Technology in Stockholm
System Source Computer Museum based in Hunt Valley, Maryland, featuring multiple Cray models
Valladolid Science Museum in Spain

These collections highlight the Cray-1’s pivotal role in computing history and its lasting impact on technology industries.