Cray-2
| Industry | Supercomputing |
|---|---|
| Founded | 1972 |
| Founder | Seymour Cray |
| Headquarters | Boulder, Colorado , United States |
| Products | Cray-2 supercomputer, Cray X-MP, Cray Y-MP, Cray C90, Cray-3, Cray X1 |
The Cray-2 represents a supercomputer equipped with four vector processors, developed by Cray Research beginning in 1985. Boasting a peak performance of 1.9 GFLOPS, it stood as the fastest computing system globally at its launch, succeeding the Cray X-MP. Its performance lead was later overtaken by the Cray Y-MP in 1988.
This system was Seymour Cray's inaugural commercially viable multi-CPU architecture. Previous efforts such as the CDC 8600 had been unsuccessful due to limitations in packaging emitter-coupled logic (ECL) transistors. The Cray-2 addressed these challenges by employing ECL integrated circuits arranged in an innovative three-dimensional wiring scheme to enhance circuit density.
The compact assembly produced considerable heat, which was managed through a unique cooling technique involving pressurized circulation of electrically non-conductive Fluorinert liquid through the circuitry, followed by external cooling. This distinctive "waterfall" cooling method became an emblematic feature of high-performance computing technology.
Although pioneering, the Cray-2 often fell short of consistently achieving its maximum performance and was outsold by other Cray models like the X-MP and Y-MP. As focus shifted toward developing the Cray C90, Seymour Cray eventually parted ways with the company.
Initial design
After the success of the Cray-1, Seymour Cray aimed to develop its successor. Growing dissatisfied with management restrictions by 1979, he resigned and established a new laboratory in Boulder, Colorado, with backing from Cray management. Beginning in 1980 as an independent consultant, he gathered a team to create a new design; this initial lab was later closed and replaced years afterward by a facility in Colorado Springs.
Cray’s approach combined enhanced parallelism through additional functional units, more compact packaging to minimize signal delay, and faster components to achieve higher clock frequencies. The CDC 8600 had previously demonstrated this concept by integrating four CDC 7600-like machines into a cylindrical form operating at an 8 ns cycle (125 MHz). However, its dense circuit boards led to frequent malfunctions and cooling difficulties.
By this time, most manufacturers had transitioned from discrete components to integrated circuits (ICs) to improve reliability. By the mid-1970s, IC technology enabled the Cray-1 to operate at 12.5 ns (80 MHz), outperforming the CDC 8600 because smaller ICs allowed for greater logic integration.
Despite advances in IC design, mechanical constraints prevented further size reduction. To realize a tenfold speed increase over the Cray-1, system complexity needed to rise significantly. The solution revisited multi-processor designs combined with higher clock speeds and increased density but necessitated novel thermal management solutions.
Another significant challenge was bridging the widening speed disparity between processors and main memory. Earlier systems relied on auxiliary computers to stream data into memory during processor execution—a technique that became ineffective as memory sizes expanded and processors accelerated. Incorporating four processors intensified this bottleneck.
To address this issue, the Cray-2 introduced a Local Memory—a 16 KWord ultra-fast memory block directly linked to four "background processors" via high-speed connections. A dedicated "foreground processor" controlled data transfer from main memory over gigabit channels per CPU—an improvement over earlier designs with fewer channels—and managed instruction delivery through eight 16-word buffers instead of monopolizing cache pathways.
Main memory was divided into quadrants allowing concurrent access, enabling programmers to distribute data for parallel processing tasks. Although configuring this scatter/gather mechanism introduced overhead and occasional latency during stride conflicts (notably with power-of-two FFT algorithms), larger memory capacities permitted straightforward solutions such as padding arrays to evenly distribute access patterns.
Dense circuit boards and innovative design solutions
Initial versions of the Cray-2 utilized large circuit boards densely populated with integrated circuits, complicating soldering processes and still falling short of the desired performance benchmarks. After roughly two years of development, Cray contemplated terminating the project and disbanding the team. Nevertheless, Les Davis, a former associate, maintained the project at a reduced priority level with a smaller crew.
Half a year later, Cray unveiled a significant innovation: rather than using a single large board, each "card" was designed as a three-dimensional stack consisting of eight circuit boards linked via pins known as "pogos" or "z-pins," resulting in a compact stack approximately 30 mm tall. Achieving this high component density necessitated immersion cooling employing 3M’s inert liquid Fluorinert, which was circulated under pressure through the modules and cooled by water-based heat exchangers. Development on this approach resumed vigorously in 1982.
At the same time, the Cray X-MP, developed under Steve Chen’s leadership, presented internal competition. To address this challenge as well as newer Japanese machines resembling the Cray-1, the Cray-2’s memory architecture was substantially upgraded in both capacity and bandwidth. By its delivery in 1985, delays meant that most performance improvements derived from enhanced memory speed, positioning it primarily for users requiring extensive data processing capabilities.
The original Cray-2 incorporated 256 MWords of physical memory—surpassing the combined memory of all earlier Cray systems—allowing more detailed three-dimensional simulations without dependence on slower virtual memory.
Applications and successors
The Cray-2 was chiefly developed to serve the United States Departments of Defense and Energy, with an emphasis on nuclear weapons research and oceanographic sonar technology. The first Cray-2 (serial number 1) was installed at the National Magnetic Fusion Energy Computer Center at Lawrence Livermore National Laboratory for unclassified energy studies. It also supported civilian organizations such as NASA Ames Research Center, academic institutions, and global corporations. For example, automotive manufacturers like Ford and General Motors employed the Cray-2 to run intricate Finite Element Analysis models for vehicle body structures and to perform virtual crash simulations prior to manufacturing.
Although intended as a precursor to the Cray-3, only one Cray-3 unit was ever constructed due to development challenges, and it was never commercially sold. Its conceptual successor is considered to be the Cray X1, which was later marketed by Cray.
Comparison with subsequent computing systems
In 2012, Piotr Luszczek demonstrated that an iPad 2 could replicate the historical performance level of the Cray-2 using an embedded LINPACK benchmark.
Trivia
Commonly referred to as "Bubbles" because of its liquid cooling system, the Cray-2 inspired humorous references involving “No Fishing” signs and plastic fish placed inside its heat exchanger tank. The system consumed between 150 and 200 kW of electrical power. Investigations at Lawrence Livermore National Laboratory during the early 1990s revealed that its cooling fluid—a perfluorinated polyether—could degrade into perfluoroisobutylene, a highly toxic gas. Cray created a poster showcasing the transparent “bubble chamber” for visual effect while joking that any fluid spill would necessitate evacuation. The fluid’s manufacturer subsequently developed a catalytic scrubber to neutralize this hazardous byproduct.
Each vertical logic module stack was positioned above power modules supplying 5-volt busbars capable of delivering approximately 2200 amps. The Cray-2 received power from two motor-generator sets converting 480 V three-phase electricity.