Cray-3/SSS
| Industry | Supercomputing, Computer hardware |
|---|---|
| Fate | Filed for Chapter 11 bankruptcy on March 24, 1995 |
Key people | Ken Iobst (engineer), Mark Norder, Jennifer Schrader |
| Products | Cray-3/SSS (Super Scalable System) |
The Cray-3/SSS (Super Scalable System) represented a pioneering effort in massively parallel supercomputer development, integrating a dual-processor Cray-3 with an innovative SIMD processing unit embedded directly within the system's main memory. Subsequently, it was suggested as an enhancement for the Cray T90 series under the designation T94/SSS; however, there is no confirmation that this version was ever manufactured.
Design
The inception of the SSS initiative occurred when Ken Iobst, an engineer at the Supercomputing Research Center, devised a new method for parallel computation. Previous massively SIMD architectures, such as the Connection Machines, relied on numerous simple processors each with local memory connected via comparatively slow networks, which created performance bottlenecks limiting their practical use.
Iobst’s approach utilized the Cray-3’s rapid scatter/gather mechanism to transfer data, eliminating dependence on separate networking systems and offering potential performance gains several magnitudes greater than those achieved by systems built from standard hardware components. The architecture maintained a complete Cray-3 CPU, allowing dynamic selection between SIMD and vector instructions based on processing requirements.
Given that the Cray-3 served as a high-performance vector processor, the SIMD units were designed to execute only fundamental instructions. The distinctive SSS design incorporated these processors directly inside the SRAM chips. Normally, RAM chips access data in parallel across rows and assemble it into 32- or 64-bit words for CPU processing. In contrast, each SRAM chip in SSS contained single-bit processors that operated simultaneously along entire columns—enabling data retrieval speeds approximately 100 times faster than conventional methods. Coupled with the scatter/gather network’s velocity, this facilitated scalability far exceeding that of traditional SIMD machines.
Each processor received two instructions every 200 nanoseconds, effectively functioning at a clock rate of 10 MHz. A fully configured system housing 1,024,000 processors was projected to achieve a total computational throughput of 32 TFlops.
Construction
In August 1994, Cray Computer Corporation (CCC) was commissioned by the NSA to develop a design comprising 512,000 processors, with each RAM chip containing 2,048 processors. National Semiconductor was selected to manufacture Iobst’s design, while Mark Norder and Jennifer Schrader worked on optimizing it for production readiness.
The initial half of the system, featuring 256,000 processors, was successfully operated on March 2, 1995.
(On March 24, 1995, Cray Computer Corporation filed for Chapter 11 bankruptcy.)