Cray-3
| Industry | Supercomputers |
|---|---|
| Founded | 1988 |
| Founder | Seymour Cray |
| Fate | Filed for bankruptcy in 1995 |
| Headquarters | Colorado Springs, Colorado , United States |
| Products | Cray-3, Cray-4 (prototype) |
The Cray-3 represented a vector processor supercomputer designed by Seymour Cray as the successor to the Cray-2. It was one of the pioneering systems to employ gallium arsenide (GaAs) semiconductors extensively, incorporating hundreds of custom-designed IC chips within its CPU. The intended computational power aimed for approximately 16 GFLOPS, which was about twelve times faster than the Cray-2.
Work on the Cray-3 commenced in 1988 at the Cray Research (CRI) facility located in Chippewa Falls, Wisconsin. Later that year, to unify project efforts, the development team relocated to a new laboratory in Colorado Springs, Colorado. Shortly thereafter, the corporate office based in Minneapolis decided to discontinue Cray-3 development to prioritize the Cray C90 project. In 1989, responsibility for the Cray-3 initiative transferred to Cray Computer Corporation (CCC).
The initial purchaser, Lawrence Livermore National Laboratory, withdrew its order in 1991, which led to several executive resignations. Although the first Cray-3 system was completed in 1993, it failed to attract additional buyers and was subsequently loaned to the National Center for Atmospheric Research in Boulder. CCC filed for bankruptcy in May 1995, marking the end of the Cray-3's operational life.
After delivering the Cray-3, Seymour Cray began developing the related but enhanced Cray-4, which never underwent testing prior to CCC’s financial collapse. The Cray-3 was the final design completed by Cray himself; following CCC’s demise, he established SRC Computers focused on parallel processing architectures but passed away in 1996 before launching any new products.
Background
Seymour Cray initiated design work on the Cray-3 in 1985 after the production release of the Cray-2. His objective was to achieve a twelvefold improvement in performance over the Cray-2—surpassing his usual goal of a tenfold increase. To reach this target, he concentrated on three key approaches: expanding parallelism through additional execution units, employing more compact packaging to minimize signal latency, and utilizing faster components to raise clock frequencies—although traditionally he had been more conservative about increasing clock speed.
In terms of packaging innovations, Cray enhanced the three-dimensional IC packaging concept originally introduced with the Cray-2. The aim was to restrict wire lengths to under , allowing the CPU to fit within a compact volume of , roughly one-third the size of its predecessor’s CPU. This reduction shrank overall system dimensions by a factor of 27 while enhancing performance.
Yet, improvements in packaging alone were insufficient for achieving a twelvefold speed increase; advancements at the chip level were also necessary. Silicon transistor switching speeds were approaching their physical limits at around 4.1 nanoseconds (244 MHz), yielding at most a doubling in speed. Consequently, Cray chose to adopt GaAs technology due to its potential for faster switching and lower power consumption. Although earlier GaAs fabrication challenges had prevented its use in the Cray-2, by the mid-1980s it became a feasible option. Because of limited commercial investment in GaAs at that time, Cray supported GaAs chip manufacturer GigaBit Logic as an internal supplier.
By November 1988, Cray anticipated that performance improvements would stem from a threefold boost via GaAs circuitry combined with a fourfold increase from additional processors. To address multiprocessing bandwidth limitations encountered with the Cray-2, the Cray-3 implemented an enhanced multiprocessing architecture derived from the Cray Y-MP, aiming for throughput around 8000 MIPS or 16 GFLOPS.
Development
Originally planned for release in 1991, the Cray-3 emerged during a period when the supercomputer industry was experiencing a slowdown, with annual growth declining from 50% in 1980 to just 10% by 1988. At the same time, Cray Research was advancing the Y-MP, a more powerful multi-processor system that evolved from the initial Cray-1. To concentrate resources, the Cray-3 initiative was moved to a new research facility in Colorado Springs, Colorado, supported by Cray himself.
By 1989, as deliveries of the Y-MP commenced and CRI progressed toward the C90 model, management reduced focus on the Cray-3 project after only 25 units of the Cray-2 had been sold. In November 1988, the Colorado Springs laboratory was spun off as Cray Computer Corporation (CCC), with CRI maintaining a 10% stake and providing $85 million to fund development efforts. Although Cray was not an equity holder, he contributed under contract. The new company encountered delays in relocating due to CRI holding onto the original lease of the facility.
Progress on the Cray-3 fell behind schedule by 1991. Development slowed further when Lawrence Livermore National Laboratory canceled its order in favor of acquiring the C90. This led to several executive departures, including the CEO. CCC then pivoted toward targeting customers interested in smaller configurations comprising four to eight processors.
The only production unit (serial S5, nicknamed Graywolf) was loaned to NCAR in May 1993, outfitted with four processors and a shared memory capacity of 1 GB. However, technical problems arose, including issues with static RAM reliability and a flaw in the square root calculation that caused an error approximately once every 60 million operations. Additionally, one of the CPUs demonstrated instability.
After investing roughly $300 million in funding, CCC filed for bankruptcy in March 1995; Graywolf was promptly retired by NCAR. In total, seven system cabinets ("tanks," numbered S1 through S7) were constructed—most being smaller two-processor machines. Three of these tanks were later adapted for use in the Cray-4 project, which featured 64 enhanced CPUs operating at 1 GHz within a more compact design. Another tank served as a platform for the Cray-3/SSS initiative.
The downfall of the Cray-3 mirrored broader political and technological shifts: the dissolution of the Warsaw Pact and conclusion of the Cold War significantly reduced demand for supercomputers. Moreover, market preferences shifted toward massively parallel (MP or MPP) architectures, which Cray openly criticized as unproven and challenging to program effectively. He remained skeptical about their widespread adoption during his lifetime.
Logical design
The Cray-3’s architecture incorporated a foreground processing system, up to 16 background processors, and a shared common memory capacity reaching up to 2 gigawords (equivalent to 16 GB). The foreground processor managed input/output operations and overall system control, utilizing a 32-bit CPU alongside four synchronous data channels designed for mass storage and network interfaces—primarily connected via HiPPI links.
Each background processor consisted of three components: a computation section, a control section, and a high-speed local memory of 16 kilowords (128 kB) intended for temporary storage. The computation section executed 64-bit scalar calculations, as well as floating point and vector arithmetic. Meanwhile, the control section oversaw instruction buffering, memory management, and maintained a real-time clock.
The common memory employed silicon-based CMOS SRAM, arranged into octants containing 64 banks each, with support for up to eight such octants. Each memory word was composed of 64 bits plus eight bits dedicated to error-correction, enabling an aggregate bandwidth of 128 GB per second.
CPU architecture
The Cray-3's central processing unit consisted of modules that housed multiple circuit boards densely populated with bare GaAs semiconductor chips. These chips were bonded using ultrasonic gold wire directly onto roughly 1-inch square substrates, which were then sandwiched between two wiring board layers, forming compact submodules stacked four layers high to create a three-dimensional circuitry structure.
In contrast to the Cray-2, the Cray-3's modules featured edge connectors. A single module was constructed from sixteen submodules arranged in a 4×4 grid, resulting in a unit of . Despite sophisticated packaging techniques, the circuit integration density reached only about 96,000 gates per cubic inch—relatively modest compared to contemporary CPUs of the 1990s that contained millions of gates per square inch.
A processor was assembled by stacking and interconnecting thirty-two such modules using twisted-pair wiring. Running at a clock cycle of 2.11 ns (equivalent to 474 MHz), each processor delivered nearly 0.948 GFLOPS, while a system with sixteen processors could theoretically attain up to 15.17 GFLOPS. Achieving this high throughput depended on rapid access to main memory, which supported burst transfer rates as high as 8 GB/s per processor.
Mechanical engineering
The Cray-3's modules were encased within an aluminum enclosure referred to as a "brick" and cooled through immersion in liquid fluorinert, following the approach pioneered by the Cray-2. A configuration comprising four processors alongside 64 memory modules drew approximately 88 kW of electrical power. The entire system occupied a footprint measuring roughly tall, front-to-back, and just over wide.
Systems containing up to four processors were housed beneath a translucent bronzed acrylic cover positioned atop a cabinet measuring wide, deep, and high. This cabinet incorporated memory units below and power plus cooling infrastructure at its base. For larger configurations with eight or sixteen processors, an octagonal cabinet design was planned. Overall, the Cray-3’s physical size was considerably reduced compared to that of the Cray-2.
Besides the main cabinet, one or two system control pods—known as "C-Pods"—each measuring square and high, contained power management and cooling control equipment.
System configurations
The officially documented Cray-3 system variants included:
| Model | Processors | Memory (Mwords) | I/O Modules |
|---|---|---|---|
| Cray-3/1-256 | 1 | 256 | 1 |
| Cray-3/2-256 | 2 | 256 | 1 |
| Cray-3/4-512 | 4 | 512 | 3 |
| Cray-3/4-1024 | 4 | 1024 | 3 |
| Cray-3/4-2048 | 4 | 2048 | 3 |
| Cray-3/8-1024 | 8 | 1024 | 7 |
| Cray-3/8-2048 | 8 | 2048 | 7 |
| Cray-3/16-2048 | 16 | 2048 | 15 |
Software environment
The Cray-3 ran the Colorado Springs Operating System (CSOS), which was adapted from Cray Research’s UNICOS version 5.0 but reimplemented in standard C without employing the Portable C Compiler extensions characteristic of UNICOS.
Its software package featured vectorizing compilers for both FORTRAN and C, along with support for the X Window System, Network File System (NFS), and a TCP/IP protocol stack—much of which was derived from software developed by Cray Research.