Cray MTA
| Company type | Supercomputer architecture |
|---|---|
| Industry | Computing |
| Predecessor | Tera MTA |
| Products | Cray MTA-1, Cray MTA-2, Cray MTA-3, Cray MTA-4 |
The Cray MTA, previously known as the Tera MTA, represents a supercomputer design that supports thousands of autonomous threads, enabling fine-grained communication, synchronization, and tolerance to latency in irregular computational tasks.
Each MTA processor (CPU) incorporates a high-speed ALU equipped with multiple independent register sets, each dedicated to executing a separate thread. For instance, the Cray MTA-2 can handle 128 threads per CPU/ALU. All MTA processors employ a barrel processor architecture that switches threads every cycle; threads that are stalled are bypassed to optimize ALU usage. When a thread issues a memory read, it stalls until the requested data is retrieved, while other threads continue processing. This high degree of concurrency ensures the ALUs remain active by masking the latency of blocked threads. The memory system leverages full/empty bits to guarantee proper sequencing—threads attempting to read from an array wait until the data is available—facilitating fine-grained interleaving and simplifying programming. Furthermore, physical addresses are randomized across memory banks to reduce contention.
The MTA emphasizes ease of porting code combined with robust performance. A parallelizing FORTRAN compiler can deliver strong results on certain applications with minimal manual tuning. When optimization is necessary, the fine-grained synchronization model enables developers to craft straightforward yet efficient code. Another critical design goal is program scalability, where increasing CPU count nearly doubles throughput—addressing scalability challenges often seen in other high-performance architectures.
Distinctively, the MTA supports efficient interleaving of multiple workloads simultaneously, unlike conventional supercomputers typically dedicated to single tasks. Idle threads can be reassigned to other jobs with minimal interference on primary computations.
Implementations
As of 2009, there have been three deployed MTA models and one planned:
- MTA-1 – A GaAs-based processor installed at the San Diego Supercomputer Center, featuring four processors totaling 512 threads.
- MTA-2 – A CMOS processor located at the Naval Research Laboratory, reported to have stability issues and was not serviceable due to security constraints.
- MTA-3 – Utilizes the same CPU as MTA-2 but incorporates a more cost-effective, slower network interface. Approximately six Cray XMT systems sold by 2009 employ this variant.
- MTA-4 – Scheduled for 2009, architecturally similar but with reduced data caching and an enhanced network interface compared to MTA-3.
Performance
Due to limited installations and reliance mainly on MTA-2 benchmarks, comprehensive performance evaluations remain constrained.
A dual-CPU MTA-2 system achieves performance on par with a two-processor Cray T90. In ray tracing workloads, a four-CPU MTA-2 outperforms a four-CPU Cray T3E by roughly five times, with scaling efficiency from one to four CPUs yielding a 3.8x speedup on the MTA compared to 3.0x on the T3E.
Architectural considerations
The MTA design includes numerous register sets, which leads to slower register access speeds. Although concurrency generally conceals latency, performance for individual threads degrades when fewer than 21 threads run per CPU, as instructions require 21 cycles each.
The early MTA versions (-1, -2, -3) exclude data caches to simplify CPU design and eliminate cache coherence complexities. This approach necessitates very high memory bandwidth because all threads access memory directly; memory operations experience significant latency (150–170 cycles). The forthcoming MTA-4 introduces a non-coherent cache intended for read-only or unshared data segments, relying on software mechanisms for coherence when threads migrate between CPUs. Selective use of caching can reduce contention and enhance performance in concurrent workloads.
Synchronization relies on polling with timeouts; when threads are descheduled due to waiting, they are swapped out allowing others to execute. However, this method may degrade performance if critical-path threads are delayed.
In summary, the MTA architecture excels at tolerating latency and managing irregular computations when ample concurrency is present, though it may be underutilized in workloads characterized by predictable latency patterns.