DEC 4000 AXP
| Company type | Product line |
|---|---|
| Industry | Computer hardware |
| Founded | November 10, 1992 |
| Founder | Digital Equipment Corporation |
| Fate | Replaced by AlphaServer 2000 and 2100 models in late 1994 |
| Products | Departmental servers based on 64-bit Alpha AXP architecture |
| Parent | Digital Equipment Corporation |
The DEC 4000 AXP represents a line of departmental server computers created by Digital Equipment Corporation, launched on November 10, 1992. These machines were among the earliest to utilize the 64-bit Alpha AXP architecture, operating on Digital's OpenVMS AXP or OSF/1 AXP platforms.
By late 1994, the DEC 4000 AXP was replaced by the AlphaServer 2000 and 2100 models within the departmental server category.
Models
The DEC 4000 AXP lineup includes two variants:
- Model 6x0, known internally as Cobra: equipped with 160 MHz DECchip 21064 (EV4) processors, each featuring a 1 MB L2 cache.
- Model 7x0, referred to as Fang: introduced in October 1993, this model incorporates 190 MHz DECchip 21064 CPUs with a larger 4 MB L2 cache per processor.
The placeholder 'x' in these model numbers indicates configurations with either one or two microprocessors.
Description
Supporting dual-processor symmetric multiprocessing (SMP), the DEC 4000 AXP is housed in either a BA640 half-height cabinet or a BA641 rackmount unit measuring 19 inches. Both chassis include two backplanes: one for the system and another for storage. The system backplane can hold one or two CPU boards, between one and four memory boards, an I/O board, and up to six Futurebus+ Profile B expansion modules. The storage backplane accommodates from one to four fixed media bays plus a slot for removable media.
CPU module
There are two types of CPU modules: the KN430 (B2001-BA) used in the Model 600 series, featuring a 160 MHz DECchip 21064 with a 1 MB L2 cache; and the B2012-AA for Model 700 series, which utilizes a faster 190 MHz DECchip 21064 and includes a 4 MB L2 cache. Each CPU board contains two C³ (Command, Control and Communication) ASICs responsible for tasks such as managing the B-cache and interfacing with the wide 128-bit address/data system bus that connects CPU, memory, and I/O components. These ASICs were manufactured using a 0.8-micrometer semiconductor process.
Memory module
The MS430 memory module offers sizes ranging from 32 MB up to 512 MB. Memory is structured into four banks of 280 bits each; out of these, 256 bits are allocated for data storage while the remaining 24 bits handle error detection and correction (EDC). The EDC circuitry is capable of identifying and correcting single-bit faults as well as common multi-bit errors.
This memory employs surface-mounted DIP-style DRAM chips with capacities of 1, 4, or16 megabits positioned on both sides of the module. Two CMIC ASICs govern memory control and facilitate communication with the system bus—each ASIC oversees half of the memory bus alongside system bus interactions. These CMOS-based ASICs come in a compact 299-pin PGA package.
Physically matching the CPU board's dimensions, the memory module connects to the backplane through two connectors with 129 pins each plus four connectors carrying 24 pins each.
I/O module
The DEC 4000 AXP utilizes the KFA40 I/O module, which is its largest hardware element and comes in two configurations. One version includes four SCSI-2 channels along with two Ethernet interfaces; the alternative model provides four DSSI/SCSI channels coupled with a single Ethernet port. Although this second variant offers half the bandwidth compared to the SCSI-2 buses of the first model, DSSI’s enhanced capabilities make it suitable for specific use cases. Aside from this difference, both versions share largely identical designs.
Standard features encompass an extra SCSI-2 channel dedicated to removable media devices, a Zilog 85C30 Serial Communications Controller (UART) providing two serial ports, a Dallas Semiconductor DS1287 real-time clock chip, and most of the firmware required by the DEC 4000 AXP. Two IONIC ASICs handle Futurebus+ management and link the I/O module to the main system bus. Ethernet connectivity is delivered by the TGEC (Third Generation Ethernet Chip, DC253), while SCSI/DSSI operations rely on four NCR 53C710 controllers supported by DSSI drivers in the second configuration.
The majority of peripheral devices interface through the local I/O "Lbus," which is a multiplexed bus carrying both address and data signals at a width of 32 bits.
Storage
The DEC 4000 AXP features four dedicated fixed media bays, each capable of housing either a single 5¼-inch device or up to four 3½-inch drives. Additionally, it includes a compartment designed for removable media such as CD-ROM drives and tape drives. To increase storage capacity, external storage units can be connected through an external SCSI interface.
Expansion
Expansion capabilities are provided via Futurebus+ Profile B, which offers six slots and supports maximum data transfer speeds reaching 160 MB/s.
Enclosures
The BA640 chassis measures 49.9 cm (20 in) in width, 88.3 cm (35 in) in height, and 77.5 cm (31 in) in depth, with a maximum weight of 124 kg (275 lb). The BA641 rackmount enclosure is designed to fit standard 19-inch racks, measuring 48.26 cm (19 in) wide, 44.4 cm (17.5 in) high, and 75.7 cm (29.8 in) deep including mounting hardware, and weighs about 65.7 kg (146 lb).