Alpha 21064

Digital Equipment Corporation
Company type	Public
Industry	Computer hardware, Microprocessors
Founded	November 11, 1957; 69 years ago in Hudson, Massachusetts, United States
Headquarters	Hudson, Massachusetts, United States
Products	Alpha 21064 microprocessor

The Alpha 21064 is a microprocessor created and produced by Digital Equipment Corporation, implementing the Alpha (initially Alpha AXP) instruction set architecture (ISA). Originally launched as the DECchip 21064 before its 1994 renaming, it is also referred to by the codename EV4. Announced in February 1992 and reaching mass availability by September of the same year, the 21064 marked Digital's inaugural commercial microprocessor utilizing the Alpha ISA. Its successor, the Alpha 21064A, arrived in October 1993, followed by the Alpha 21164 in 1995.

History

The first Alpha processor was a prototype chip known as EV3, manufactured using Digital’s 1.0-micrometre CMOS-3 fabrication technology. This early version lacked a floating point unit and contained only 1 KB of cache memory, serving primarily to validate advanced circuit design approaches and aid in firmware and operating system development.

The production-ready chip, designated EV4, was produced with Digital’s refined 0.75 μm CMOS-4 process. The design team was led by micro-architects Dirk Meyer and Edward McLellan—McLellan concentrated on issue logic, while Meyer oversaw other critical components—with Jim Montanaro managing circuit implementation. The EV3 powered the Alpha Demonstration Unit (ADU), a multiprocessor platform used for software development ahead of EV4’s release.

The 150 MHz sample of the 21064 was introduced at the 39th International Solid-State Circuits Conference (ISSCC) in February 1992. Initial pricing was set at $3,375 per unit for orders of 100 chips, dropping to $1,560 for orders exceeding 1,000 units. Full-scale shipments commenced in September 1992.

By February 1993, prices for the 150 MHz model had fallen to $1,096 per unit for orders over 1,000. On February 25th, a 200 MHz variant was announced with sample kits priced at $3,495 and volume pricing at $1,231 per unit for purchases above 10,000 units. Mass shipments began in August 1993. This release triggered a price reduction for the 150 MHz version to $853 per unit for large orders.

Following the September 1993 debut of the Alpha 21066 and Alpha 21068 models, Digital adjusted pricing on existing chips and introduced a 166 MHz option priced at $499 per unit for orders of at least 5,000 units. Concurrently, the 150 MHz version’s price decreased to $455 under similar order quantities.

On June 6, 1994, prices were further lowered: the cost of the 200 MHz chip dropped by 31% to $544 to better compete with Intel's Pentium running at 60 MHz, while the 166 MHz model saw a 19% reduction to $404 per unit for large volume purchases effective July.

Digital Equipment Corporation remained the exclusive manufacturer of the Alpha 21064 without any secondary sourcing agreements. Production took place at Digital’s fabrication plants located in Hudson, Massachusetts and South Queensferry, Scotland.

Users

The primary applications for the 21064 were in high-performance workstations and server systems. Notable adopters included:

Aspen Systems with their Alpine workstation series
Carrera Computers’ Hercules 150, Hercules 200, and Pantera II workstation lines
Cray Research, which utilized the 150 MHz variant within its Cray T3D supercomputers
Digital itself deployed the chip across entry-level workstations and servers (DECpc AXP 150, DEC 2000 AXP, DEC 3000 AXP), mid-range servers (DEC 4000 AXP), and high-end server platforms (DEC 7000/10000 AXP)
Encore Computer incorporated it into their Infinity R/T high-end real-time computing systems

Performance

From its debut until 1993, the 21064 held the title of the fastest microprocessor on the market. Although IBM's multi-chip POWER2 eventually outperformed it, the 21064 remained the quickest single-chip processor until October 1993, when the 275 MHz 21064A was introduced.

Description

The Alpha 21064 is designed as a superpipelined, dual-issue superscalar CPU that processes instructions sequentially. It can dispatch up to two instructions every clock cycle through four distinct functional units: an integer unit, a floating-point unit (FPU), an address unit, and a branch unit. The integer pipeline consists of seven stages, while the floating-point pipeline extends to ten stages. The initial four stages are shared by both pipelines and are governed by the I-box.

I-box

Functioning as the control hub, the I-box manages instruction fetching, decoding, issuing, and pipeline flow control. During the first stage, it retrieves two instructions from the instruction cache (I-cache). Branch prediction is performed in the second stage utilizing either static or dynamic techniques: static prediction relies on the sign bit of branch displacement to assume backward branches are taken; dynamic prediction references a 2,048-entry, single-bit branch history table achieving roughly 80% accuracy. A mispredicted branch results in a four-cycle penalty.

Instructions undergo decoding in stage three. By stage four, the I-box evaluates resource availability and issues instructions if they can be paired. Pairing depends on read/write port availability within the integer register file. Valid pairs include an integer operation with a floating-point operation, any load/store paired with an operation instruction, an integer operation with an integer branch, or a floating-point operation with a floating-point branch. Invalid pairs include integer operations combined with floating-point stores and floating-point operations combined with integer stores. If pairing is not feasible or resources are limited, pipeline stages one through four stall.

The I-box contains two fully associative instruction translation buffers (ITBs) for converting virtual addresses to physical addresses: one eight-entry ITB for 8 KB pages and another four-entry ITB for 4 MB pages. Both employ a not-last-used replacement policy.

Execution

Execution begins at stage five for all instructions, following register file reads during stage four. From stage five onward, pipelines operate without stalling capability.

Integer unit

The integer unit processes integer instructions and comprises the integer register file (IRF) along with the E-box. The IRF includes thirty-two 64-bit registers equipped with four read ports and two write ports shared between integer and branch units. The E-box integrates an adder, logic unit, barrel shifter, and multiplier. Most integer instructions complete by stage five with a latency of one cycle; exceptions include multiply, shift, and byte manipulation instructions. Shifts and byte manipulations require two cycles due to limitations of the pipelined barrel shifter. The multiplier is not pipelined to conserve die space, resulting in variable latencies ranging from 19 to 23 cycles. Results are written back to the IRF in stage seven.

Address unit

Referred to as the "A-box," the address unit manages load and store operations concurrently with the integer unit by employing its own displacement adder for virtual address calculations. It incorporates a fully associative 32-entry translation lookaside buffer (TLB), named the data translation buffer (DTB), supporting virtual addresses up to 43 bits (8 TB) and physical addresses up to 34 bits (16 GB). Store operations utilize a four-entry by 32-byte write buffer that merges contiguous stores and postpones writes to minimize system bus traffic, thereby enhancing load performance.

Floating-point unit

The floating-point unit integrates a floating-point register file (FRF) consisting of thirty-two 64-bit registers, equipped with three read ports and two write ports, alongside the F-box which houses a floating-point pipeline and a non-pipelined divider that processes one bit per cycle.

During the fourth stage, the FRF is accessed and the data is decomposed into sign, exponent, and fraction components. For addition operations, exponent differences are computed and normalization detection begins; multiplication instructions produce a 3× multiplicand. The fifth and sixth stages handle alignment or normalization shifts along with sticky-bit computations for addition and subtraction. Multiplications utilize a pipelined, two-way interleaved radix-8 Booth algorithm array. Final addition and rounding take place in stage eight, with the results written back to the FRF at stage ten.

The floating-point pipeline exhibits a latency of six cycles. Single-precision and double-precision division operations executed by the non-pipelined divider incur latencies of 31 and 61 cycles, respectively.

Caches

The 21064 incorporates two on-chip primary caches: an 8 KB data cache (D-cache) employing a write-through policy and an 8 KB instruction cache (I-cache). Both caches are direct-mapped to enable single-cycle access and utilize 32-byte line sizes. Constructed from six-transistor SRAM cells sized at 98 μm², these caches are arranged as 1,024 cells wide by 66 cells tall, with the upper two rows reserved for redundancy.

An optional external secondary cache known as the B-cache supports sizes ranging from 128 KB up to 16 MB. It operates at one-third to one-sixteenth of the internal clock frequency (12.5 to 66.67 MHz when running at 200 MHz), is direct-mapped by default with a 128-byte line size configurable for larger lines, and connects via the system bus.

External interface

The external interface offers a configurable 128-bit data bus that functions at speeds between half and one-eighth of the internal clock rate (25 to 100 MHz at a 200 MHz core frequency). Systems also have the option to implement a 64-bit external interface. Accompanying this is a 34-bit address bus.

Fabrication

The 21064 chip integrates approximately 1.68 million transistors and was initially manufactured using Digital’s CMOS-4 process featuring a 0.75 μm technology node with three layers of aluminum interconnects. The EV4 die measures 13.9 mm by 16.8 mm, totaling an area of 233.52 mm². A subsequent EV4S variant employed CMOS-4S technology—a 10% optical shrink to a 0.675 μm process—reducing die dimensions to 12.4 mm by 15.0 mm (186 mm²).

Operating on a 3.3-volt power supply, the EV4 dissipates up to 30 W at a clock speed of 200 MHz, whereas the EV4S consumes between 21 W at 150 MHz and 27 W at 200 MHz.

Package

This microprocessor is enclosed within a pin grid array (PGA) ceramic package made from alumina, containing 431 pins arranged in a square measuring 61.72 mm on each side. Of these pins, 291 serve signal functions while the remaining 140 provide power and ground connections. The heatsink affixes directly onto the package through nuts secured on studs extending from a tungsten heat spreader.

Alpha 21064A

The Alpha 21064A, also known as DECchip 21064A and codenamed EV45, represents an improved iteration of the Alpha 21064 introduced in October 1993. It was produced in variants running at clock speeds of 200, 225, 233, 275, and 300 MHz. On July 6, 1994, the 225 MHz version was superseded by the 233 MHz model priced at US$788 per batch of 5,000 units—a reduction of approximately ten percent compared to its predecessor. Concurrently, pricing for the 275 MHz variant dropped by twenty-five percent to US$1,083 per five thousand units. The highest-speed model at 300 MHz was announced in October of 1995 and entered shipment by December of that year. A specialized model named the 21064A-275-PC was restricted for use with Windows NT or compatible operating systems.

As Digital’s premier Alpha microprocessor offering, the Alpha 21064A powered high-performance systems such as Digital’s DEC 3000 AXP, DEC 4000 AXP, and DEC 7000/10000 AXP series. Additional adopters included Aspen Systems with their Alpine workstation, BTG’s Action AXP275 RISC PC, Carrera Computers’ Cobra AXP275 workstation, NekoTech’s Mach 2-289-T (which was overclocked to reach speeds of up to 289 MHz), and Network Appliance’s storage solutions.

Architectural enhancements featured doubling both instruction and data caches from their original size of eight kilobytes to sixteen kilobytes each while adding parity protection for improved reliability. Floating-point division latency was reduced through an upgraded divider capable of retiring two bits per cycle on average. Branch prediction accuracy improved via an expanded branch history table containing four thousand ninety-six entries with two-bit counters.

The chip contained approximately 2.8 million transistors within a die measuring roughly fourteen point five millimeters by ten point five millimeters (152.25 mm²). It was fabricated using Digital’s fifth-generation CMOS-5 process technology with a feature size of half a micrometer (0.5 μm) incorporating four layers of aluminum interconnects.

Alpha 21066

The Alpha 21066, also known as the DECchip 21066 and internally referred to as LCA4 (Low Cost Alpha), represents a budget-friendly adaptation of the Alpha 21064 processor. It was introduced in late 1993, with mass production commencing in early 1994. The first variant operated at 166 MHz and was priced at US$385 for orders of 5,000 units. Subsequently, a slower 100 MHz version tailored for embedded applications was released in late 1994, with shipments beginning mid-1995. Notably, The Microprocessor Report identified it as the pioneering CPU to incorporate a PCI controller on-chip.

Designed primarily for affordable Windows NT-based personal computers, Digital implemented the Alpha 21066 in Multia client systems, AXPpci33 OEM motherboards, and AXPvme single-board computers. External manufacturers also adopted this processor, including Aspen Systems with their Alpine workstation, Carrera Computers’ Pantera I workstation, NekoTech’s Mach1-166 PC, and Parsys’ TransAlpha TA9000 supercomputers.

Through a die shrink process, the chip integrated features beneficial for embedded markets: an on-chip B-cache and memory controller supporting ECC; a modest graphics accelerator capable of handling up to 8 MB of VRAM framebuffer; a PCI controller; and a PLL clock generator that multiplied an external 33 MHz clock signal.

The memory controller accommodated B-cache capacities ranging from 64 KB to 2 MB and supported main memory sizes between 2 MB and 512 MB. The ECC functionality provided detection of multiple bit errors alongside single-bit error correction. To minimize both cost and package dimensions, the system bus width was restricted to 64 bits—resulting in roughly a 20% decrease in bandwidth and performance, which was considered acceptable for its intended use cases.

The Alpha 21066 comprised approximately 1.75 million transistors on a die measuring 17.0 by 12.3 mm (total area of 209.1 mm²). It was manufactured using the CMOS-4S process (0.675 μm) featuring three layers of interconnects. The processor was housed in a 287-pin CPGA package measuring about 57.4 by 57.4 mm.

Alpha 21066A

The Alpha 21066A, internally designated as LCA45, is an economical variant of the Alpha 21064A announced on November 14, 1994. It debuted with models running at 100 and 233 MHz, which were available by March 1995. Initial pricing stood at $175 and $360 respectively for quantities of 5,000 units. Later on, a faster 266 MHz version was introduced.

Mitsubishi Electric became a secondary manufacturer of the 21066A under the name M36066A, marking its inaugural fabrication of Alpha microprocessors. Announced concurrently with Digital's release, Mitsubishi aimed to deliver engineering samples by December 1994 and begin volume production by September 1995, setting the price for the 233 MHz model at $490 per batch of 1,000 units.

Differing from the Alpha 21064A, the Alpha 21066A omitted the separate 16 KB instruction and data caches but added power-saving capabilities through software-managed clock frequency scaling.

Digital integrated several versions of the 21066A into product lines that had previously utilized the original 21066 processor. For example, Tadpole Technology incorporated a 233 MHz variant within its ALPHAbook 1 laptop computer.

This chip contained roughly 1.8 million transistors on a die area of about 161.32 mm², fabricated using Digital’s CMOS-5 (0.5 μm) technology with three interconnect layers. Mitsubishi produced its M36066A variant using a comparable manufacturing process.

Alpha 21068

The Alpha 21068 (DECchip 21068) was developed specifically for embedded system applications and closely resembled the design of the Alpha 21066 but operated at reduced clock speeds to lower power consumption and manufacturing costs. It was launched in September 1993 with volume shipments starting early in 1994. This model ran at a frequency of 66 MHz and featured a maximum power dissipation rating of approximately 9 watts. Initially priced at $221 per unit for orders of 5,000 pieces, Digital later reduced this price by about sixteen percent to $186 effective July of that year.

Digital deployed the Alpha 21068 in its AXPpci33 motherboard as well as AXPvme single-board computer platforms.

Alpha 21068A

The Alpha 21068A (also known as DECchip 21068A) represents a specialized embedded systems version of the Alpha 21066A, functioning at a clock speed of 100 MHz.

Chipsets

At first, the 21064 and 21064A processors did not have a dedicated standard chipset, leading Digital to depend on proprietary ASICs for system interfacing. This approach raised development expenses for original equipment manufacturers. To mitigate these challenges, Digital launched the DECchip 21070 (Apecs) chipset, which aimed to unify Alpha system integration.

This chipset family comprised two variants: the DECchip 21071, designed for workstation use, and the DECchip 21072, intended for high-performance workstations or entry-level uniprocessor servers. The primary distinction between them was in memory bandwidth and capacity: the 21071 supported a 64-bit memory bus accommodating between 8 MB and 2 GB of parity-checked memory, whereas the 21072 featured a wider 128-bit bus capable of handling up to 4 GB of ECC-protected memory.

The chipset architecture included three core components—COMANCHE serving as the B-cache and memory controller, DECADE modules implementing data slices, and EPIC acting as the PCI controller. DECADE chips organized data paths into 32-bit slices, with two chips employed in the 21071 and four in the 21072 configurations. EPIC provided a 32-bit PCI interface connected to the DECADE modules.

Introduced on January 10, 1994, with sample units available immediately and mass production commencing by mid-year, pricing was set at $90 per unit for the 21071 and $120 per unit for the 21072 based on orders of 5,000 units.

Notable adopters included Carrera Computers' Pantera workstation line along with Digital's own AlphaStation series and uniprocessor AlphaServer models.

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