DEC Firefly
| Company type | Research project |
|---|---|
| Industry | Computer hardware |
| Predecessor | MicroVAX II |
| Founded | 1984 |
| Founder | DEC Systems Research Center |
| Headquarters | United States |
| Products | Multiprocessor workstations (Firefly, VAXstation 3520/3540) |
| Parent | Digital Equipment Corporation |
The Firefly was a shared memory asymmetric multiprocessor workstation engineered by the DEC Systems Research Center, a research branch of Digital Equipment Corporation. Its first iteration incorporated up to seven MicroVAX 78032 CPUs, each with caches synchronized through the Firefly protocol to maintain memory consistency. The subsequent version upgraded these to faster CVAX 78034 processors. DEC eventually marketed this system as the VAXstation 3520/3540, internally known as Firefox.
Hardware description
The Firefly was designed as an asymmetric multiprocessor workstation housed in a rack, where only a single microprocessor had direct connectivity to the Q-Bus I/O subsystem.
Processors
The architecture consisted of a main processor board accompanied by up to three additional processor boards. Each board measured 8 by 10 inches. The main board integrated a microprocessor, floating-point coprocessor, cache memory, and Q-Bus interface logic. Secondary boards each contained two microprocessors along with their respective floating-point units and caches. Initial Firefly systems utilized the MicroVAX 78032 CPU paired with the MicroVAX 78132 floating-point coprocessor; later versions transitioned to the more powerful CVAX 78034 processors and CVAX Floating Point Chips. Communication between processor boards was facilitated by the MBus. These components were originally developed for the MicroVAX II platform, with initial considerations for Motorola 68010 CPUs.
To optimize multiprocessing, caches were direct-mapped and maintained coherence via the Firefly protocol. MicroVAX-based boards featured 16 KB caches constructed from SRAM and TTL components; CVAX-based boards expanded cache capacity to 64 KB using larger SRAM chips. Cache management logic was implemented using programmable array logic (PAL) devices.
Memory
Each processor accessed main memory through its local cache and the MBus interconnect. Memory modules attached to the MBus varied from one to four units per system. The original Firefly configuration included a single 4 MB master memory module plus up to three identical slave modules, yielding between 4 MB and 16 MB total memory. Later models employed larger 32 MB modules, increasing total capacity from 32 MB up to 128 MB. Memory access latency improved significantly, dropping from 400 nanoseconds in MicroVAX-based systems to 200 nanoseconds in those utilizing CVAX processors.
I/O
Input/output peripherals interfaced through the Q-Bus, which featured a 22-bit address range mapped onto Firefly’s broader 24-bit memory space via registers managed by the master processor. Devices performed direct memory access (DMA) operations through the main processor’s cache system. Key I/O elements comprised a monochrome display controller (MDC), buffered magnetic disk controllers such as the RQDX3, and the DEQNA Ethernet interface.
While most peripherals were standard DEC hardware, the display controller was custom-developed by Firefly engineers to satisfy stringent performance criteria. Two variants existed: color and monochrome controllers, both utilizing DMA-driven work queues in shared memory, enabling symmetric multi-processor access.
The monochrome display controller (MDC) occupied about half the footprint of a processor board and supported a resolution of 1024×768 pixels. It incorporated a 10 MHz 16-bit Am29116 microprocessor equipped with a microinstruction store of 10 KB (2,048 words of 40 bits each). A VRAM-based frame buffer sized at 1024×1024 pixels allocated approximately three-quarters of its capacity for display bitmaps, with the remainder reserved for font caching or display management tasks.
The Am29116 periodically processed DMA work queues, executing commands such as BitBlt operations within the frame buffer or transferring data between system memory and frame buffer, as well as rendering characters from cached fonts.
Display hardware also supported keyboard and mouse inputs, updating mouse coordinates and keyboard status in memory at a frequency of 60 Hz. By implementing MDC as an I/O device, multiple display controllers and monitors could be integrated into a single system.
Software
The Firefly systems operated using a software suite named Topaz, which included elements such as the Taos operating system featuring a microkernel called the Nub and the Trestle window system. Taos was compatible with the Ultrix binary interface, allowing Ultrix binaries originally compiled for MicroVAX to execute on Firefly without modification. In contrast to Ultrix, Topaz offered support for multi-threaded processes running on multiple processors and permitted simultaneous execution of both Ultrix and Topaz applications. The development of Topaz and its associated applications utilized Modula-2+, an enhanced variant of Modula-2.
Additionally, the Stanford V (operating system) was configured to run on Firefly setups comprising one CVAX and four MicroVAX-II CPUs housed within a BA123 chassis, equipped with QVSS/VCB01 graphics.
See also
- Firefly protocol – The cache coherence mechanism implemented by the Firefly.