Q-Bus
| Industry | Computer hardware |
|---|---|
| Founded | November 16, 1957 in Maynard, Massachusetts, United States |
| Headquarters | Maynard , United States |
| Products | PDP systems, MicroVAX systems, Q-bus architecture |
The Q-bus, also referred to as the LSI-11 Bus, is a bus architecture utilized in PDP and MicroVAX systems originally manufactured by Digital Equipment Corporation in Maynard, Massachusetts.
As a budget-friendly alternative to Unibus, the Q-bus employs multiplexing techniques that allow address and data signals to share the same wiring. This design choice results in a more compact and economical system while maintaining comparable capabilities.
Over successive iterations, its physical address width increased from 16 bits to 18 bits, and later to 22 bits. Additionally, block transfer modes were introduced to boost data transfer efficiency.
Main features of the Q-bus
The Q-bus architecture is composed of modules that are inserted into one or more backplane assemblies.
Similar to Unibus, it offers support for:
- Memory-mapped I/O
- Byte addressing
- A rigid master-slave device hierarchy
- Asynchronous signaling
With memory-mapped I/O, all data transactions among the CPU, memory, or I/O peripherals follow a unified protocol. The Q-bus streamlines I/O addressing through a dedicated signal line (initially labeled BBS7, later renamed BBSIO) which designates I/O address spaces.
Byte addressing treats physical addresses as individual byte locations. Due to the two-byte-wide data path, special consideration is given to address bit [0] to ensure proper alignment of byte lanes.
The strict master-slave framework permits only one device to act as bus master at any given time, initiating communication with a single slave device. Bus arbitration then determines which device gains master control next.
Asynchronous signaling implies that bus cycles vary in length and are governed by handshake signals exchanged between the master and slave devices. Timeout mechanisms are implemented to prevent excessively long cycles.
Depending on the version, the Q-bus features 16, 18, or 22 BDAL (Bus Data/Address Lines) that serve dual purposes for addressing and transferring data of either 8 or 16 bits. Later models incorporate block transfer modes that allow multiple data transfers within a single address cycle, thereby enhancing throughput.
Bus mastering priority is influenced by an I/O card's physical position relative to the bus arbitrator; cards situated closer receive higher priority access.
Interrupts are handled across four priority levels by the Interrupt Fielding Processor (IFP). Within each level, cards nearer to the IFP hold precedence. The interrupt system is vectored: the IFP reads an interrupt vector supplied by the requesting device, enabling precise identification of interrupt sources.
Physical characteristics
Q-bus components consist of printed circuit boards equipped with gold-plated edge connectors designed for insertion into backplane slots. These edge connectors are segmented into multiple "fingers," featuring four connectors per card compared to six on Unibus cards. Modules are available in double-height (two connectors wide) or quad-height (four connectors wide) formats, describing their PCB width. Quad-height modules typically accommodate CPUs, memory units, video processors, and other devices requiring substantial bandwidth. Double-height modules generally include interface cards, breakout boards, real-time clocks, ROM or microcode storage, and devices with lower bandwidth demands. Notable exceptions include certain double-height CPUs such as the LSI-11/2 and some early small-capacity memory boards.
Logic Minimization
Like the Unibus, the Q-bus employs signaling techniques designed to reduce logic complexity along the bus. It utilizes asynchronous signaling, with the bus master responsible for managing address and data de-skewing, which simplifies the design requirements for slave devices. Additionally, bus cycle timeouts are controlled by the masters. Interrupt processing is centralized within a dedicated Interrupt-Fielding Processor—commonly a PDP-11 or VAX-11—enhancing overall system efficiency.
Compatibility
The architecture and implementation of the Q-bus closely resemble those of the Unibus. Compatibility between Q-bus and Unibus peripherals is achieved through Digital and third-party adapters. Many input/output devices were produced in both Q-bus and Unibus formats, frequently differing only slightly or not at all, allowing for versatile system configurations.
Soviet Clones
Within Soviet computing systems (refer to 1801 series CPU), the Q-bus design is identified as МПИ (Магистральный Параллельный Интерфейс, meaning parallel bus interface). This variant supports up to four processors sharing the same bus while maintaining binary and electrical compatibility with the standard Q-bus. The primary distinction lies in the connector arrangement.
Cycle Types
The Q-Bus defines six fundamental transaction categories:
- DATI – Data input (master reading)
- DATO – Data output (master writing)
- DATOB – Data output (byte-level)
- DATIO – Bidirectional data transfer
- DATIOB – Bidirectional data transfer (byte-level)
- IAK – Interrupt acknowledgment
Device Types
Modules designed for the Q-Bus encompass:
- Central Processing Unit modules
- Memory modules
- Interface modules
- System modules such as grant continuity cards and connector breakout boards
Interfaces
The Q-Bus supports a range of interface cards, including dual-width modules (featuring two connector sets and occupying half a slot) and quad-width modules (with four connector sets filling a full slot). Examples include a 1 MBit Bubble memory expansion card in dual-width format, an 8K × 19 bit core memory expansion card as a quad-width module, along with DEC MicroVAX II quad-width memory modules.
External links
- HP OpenVMS :: Q-Bus Hardware at HoffmanLabs
- The Lab - Q-Bus Beispielplatine, Selbstgebaute Q-BUS Platinen at RunningServer.com (German)
- DEC STD 160: LSI-11 Bus Specification