DEC V-11
| Industry | Computer hardware |
|---|---|
| Founded | 1957 |
| Founder | Ken Olsen, Harlan Anderson |
| Headquarters | Maynard, Massachusetts , United States |
| Products | V-11 (Scorpio) miniprocessor chipset, among others |
The V-11, also known by its codename "Scorpio", is a miniprocessor chipset designed to implement the VAX instruction set architecture (ISA). It was both developed and manufactured by Digital Equipment Corporation (DEC).
History
Although the V-11 represented DEC's inaugural microprocessor design for the VAX architecture, it was the second to reach the market following the MicroVAX 78032. Released in early 1986, the chip initially ran at 5 MHz (with a 200 ns cycle time), later increasing to 6.25 MHz (160 ns cycle time). This proprietary processor was utilized exclusively in DEC’s VAX 8200, 8250, 8300, and 8350 minicomputer models, as well as in the VAXstation 8000 workstation.
At its initial 5 MHz speed, the V-11 delivered performance comparable to the VAX-11/780 superminicomputer; when operating at 6.25 MHz, it achieved approximately a 20% increase in speed.
The V-11 was developed under DEC’s Scorpio initiative, which focused on building internal expertise for designing and fabricating very-large-scale integration (VLSI) circuits. This endeavor included creating advanced computer-aided design (CAD) tools and developing the ZMOS semiconductor process—DEC’s first fully in-house fabrication technology.
Description
The V-11 employed a multi-chip architecture consisting of an I/E chip, M chip, F chip, along with five ROM/RAM chips. In contrast to the MicroVAX 78032—which implemented only a subset of the VAX instruction set—the V-11 supported the entire set of 304 VAX instructions and all 17 data types, covering everything from bytes to complex floating-point and string formats.
Communication between these chips occurred over four buses: MIB (microinstruction bus), DAL, PAL, and CAL. The MIB was a 40-bit bus with parity protection that transmitted microinstruction control signals from the control store to both the I/E and F chips. The DAL bus, also parity-protected but 32 bits wide, carried data and addresses among the I/E, M, and F chips, as well as to cache memory, backup translation buffers, and the port interface.
ROM/RAM chip
The ROM/RAM chip (DC327) contained one-fifth of the processor’s patchable control store. It featured a 16 KB read-only memory (ROM), a 1 KB random-access memory (RAM) dedicated to control store patches, and a content-addressable memory (CAM) with 32 entries. Each DC327 die measured approximately 8.74 mm by 7.24 mm and housed around 208,000 transistors while dissipating roughly 1 watt of power.
Five DC327 chips were mounted together on a single ceramic carrier inside an unusually wide Dual In-line Package (DIP), collectively constituting the complete control store for the processor. Each chip contained unique ROM data specific to its portion of the control store.
I/E chip
The I/E chip (DC328) combined several functions: an instruction buffer, microsequencer, execution unit, and mini-translation buffer (MTB). The instruction buffer held two entries of 32-bit instructions and performed prefetching to ensure smooth execution flow. The execution unit included sixteen general-purpose registers of 32 bits each in accordance with the VAX ISA, along with an arithmetic logic unit (ALU) and a shifter. The MTB served as a translation lookaside buffer (TLB) with five page table entries (PTEs)—one allocated for instructions and four for data; any misses were resolved by the M chip’s backup translation buffer (BTB). The I/E chip incorporated approximately 60,000 transistors on a die sized at 354 by 358 mils (8.99 by 9.09 mm), occupying an area of about 81.76 mm² and consuming around 5 watts of power.
M chip
The M chip (DC329) is responsible for handling memory management and interrupt processing, containing BTB tags, cache tags, and internal processor registers. It also delivers VAX-specific I/O capabilities and generates the clock signal for the chipset.
To address MTB misses, the BTB utilizes 512 PTEs—split evenly with 256 allocated to system space and 256 to process space—structured as 128 BTB tags within the M chip and implemented using external RAM. The chip features 26 internal registers that microcode employs to facilitate multi-cycle instruction execution. With a transistor count of 54,000, the M chip occupies a die measuring 339×332 mil (8.61×8.43 mm) or 72.61 mm², and it consumes 3 watts of power.
F chip
The F chip (DC330) incorporates the floating-point unit (FPU), supporting the majority of VAX floating-point instructions along with f_floating, d_floating, and g_floating data formats. Additionally, it performs integer multiplication and division operations. Instruction opcodes are received from the I/E chip; operands are fetched via the DAL bus from either memory or registers, with results returned through the same channel. The F chip contains 29,600 transistors on a die sized 341×288 mil (8.66×7.32 mm), totaling 63.36 mm² in area and dissipates 2.5 watts.
Originating from the J-11 microprocessor’s floating-point accelerator used in the PDP-11, the F chip replaced an initially planned new design to streamline development and hasten completion during simultaneous work on the MicroVAX 78032.
Cache
The V-11 system incorporates an external primary cache of 8 KB capacity, employing physical addressing with cache blocks sized at 64 bytes.
Physical
Across nine separate dies, the V-11 chipset integrates a total of 1,183,600 transistors and is manufactured using Digital’s ZMOS process—a 3.0 μm NMOS fabrication technology featuring two layers of metal interconnects.