IBM 801
| Company type | Internal project / processor design |
|---|---|
| Industry | Computer processors / Computer hardware |
| Founded | 1970s |
| Founder | John Cocke (lead) |
| Headquarters | Yorktown Heights , United States |
| Products | 801 CPU, IBM ROMP microprocessor, IBM RT PC, IBM 9370 mainframe processors, IBM 3090 channel controllers |
The 801 was an innovative central processing unit (CPU) created by IBM during the 1970s and is acknowledged as the pioneering design of a modern RISC processor. It performed all calculations exclusively using processor registers, removing the extensive variety of addressing modes commonly found in CISC architectures. Originally intended for a telephone switch, it subsequently became the basis for a minicomputer and several mainframe systems. The initial 24-bit 801 design was eventually replaced by 32-bit versions, with the 24-bit variant remaining in use only until the early 1980s.
Though initially perceived as a straightforward processor unlikely to compete with IBM’s sophisticated systems such as the System/370, comprehensive performance analyses from customers demonstrated that its simplified design surpassed the capabilities of powerful conventional CPUs. Incorporating RISC principles into existing machines like the S/370—prioritizing register-based operations instead of intricate opcodes—resulted in a twofold increase in performance. The complexity inherent in older CISC architectures produced slower, more expensive systems encumbered by instructions seldom utilized. This outcome validated the RISC methodology and shaped all future IBM platforms.
John Cocke, who led the 801 initiative, received distinguished accolades including the Turing Award (1987), National Medal of Technology (1991), and National Medal of Science (1994).
Initial concept
In 1974, IBM investigated designing a telephone switch capable of managing one million calls hourly (approximately 300 calls per second). This required roughly 20,000 instructions per call and an estimated throughput of 12 MIPS—about four times faster than their leading system at that time, the IBM System/370 Model 168 (approximately 3 MIPS).
The team at the Thomas J. Watson Research Center, headed by John Cocke, engineered a processor specifically to meet these demands by eliminating unnecessary components such as a floating-point unit. Their focus was exclusively on instructions manipulating rapid internal processor registers rather than slower main memory accesses. This approach resulted in a streamlined processor concept capable of achieving the targeted performance.
Although the telephone switch project was discontinued in 1975, IBM persisted with this versatile design, naming it "801" after their facility. Analyzing typical minicomputer workloads through extensive IBM performance data revealed that over half of execution time centered on only five instructions: memory load/store, fixed-point addition and comparison, plus conditional branching. This confirmed that the simplified RISC architecture was well-suited for wider applications beyond telecommunications.
Arguments against microcode use
This finding posed a challenge to the dominant processor design philosophy based on microcode, which IBM extensively employed in their System/360 line. The 360s and subsequent 370s delivered various performance tiers while running identical machine language code. High-end models implemented many instructions directly in hardware; lower-end models simulated these instructions using microcode. This strategy maintained a uniform application binary interface across products, enabling customers to upgrade hardware without modifying software.
Microcode allowed simpler processors to support numerous instructions and diverse addressing modes. For instance, an ADD instruction had several forms depending on operand locations; microcode decomposed these into internal steps such as loading values into registers before performing addition. The objective was an orthogonal instruction set, providing every addressing mode for all instructions.
The 801 team noticed that compilers generally chose a single instruction variant—usually the one implemented in hardware on low-end machines—to optimize performance across different platforms. Although other variants could execute faster on specific hardware, compiler complexity prevented their widespread use. Consequently, most instructions in the set remained unused within compiled code.
The central insight from the 801 project was:
Embedding microcode between a computer and its users introduces costly overhead when executing the most frequently used instructions.
Microcode adds decoding steps prior to execution. Eliminating it permits faster instruction processing by shifting complex instructions into compiler-generated sequences rather than microcoded routines. This transformation could significantly enhance machine speed.
A potential drawback was program size growth since some single microcoded instructions (such as adding two memory-resident values) required multiple explicit instructions on the 801. This might increase memory access latency and impair performance. However, continuous improvements in both hardware design and compiler technology yielded program sizes comparable to those targeting the 370.
Initial Deployments
The first iteration of the 801 architecture incorporated sixteen 24-bit registers and did not support virtual memory. Its instruction format employed two operands, commonly expressed as A = A + B, instead of the three-operand style A = B + C. The CPU, completed by mid-1980, was constructed using Motorola MECL-10K discrete components mounted on wire-wrapped boards. Operating at a clock speed of 66 ns (approximately 15.15 MHz), it delivered around 15 MIPS.
IBM integrated the 801 architecture into multiple products, such as channel controllers for S/370 mainframes like the IBM 3090, various networking hardware, and as a vertical microcode execution unit within the 9373 and 9375 processors from the IBM 9370 mainframe series. The foundational 801 design also served as the basis for the IBM ROMP microprocessor, which powered the IBM RT PC workstation and several IBM Research experimental platforms. A 32-bit variant called Iliad was created for the ultimately unsuccessful Fort Knox midrange system initiative.
Subsequent Enhancements
Initially tailored for systems with limited functionality, the 801 lacked built-in hardware support for virtual memory, relying instead on software implementations in its early versions. To appeal to a wider market, hardware-based virtual memory became a necessity. Moreover, as the industry gravitated toward 32-bit computing during the 1980s, IBM aimed to evolve the 801 to meet these emerging standards.
Shifting to a 32-bit instruction format enabled inclusion of a third register operand, addressing inefficiencies inherent in the two-operand design where output overwrote inputs and necessitated additional memory accesses. This upgrade also doubled the register count from sixteen to thirty-two, enhancing code efficiency without substantially increasing program length despite longer instruction sizes.
Additional improvements encompassed instructions optimized for handling "packed" string data and operations involving binary-coded decimal, supported by dedicated adders. When executed as a simulator on the IBM 370 platform, compiled programs frequently surpassed native 370 machine code generated from PL/I in performance due to superior register utilization and fewer memory operations. The experimental "PL.8" compiler further underscored these advantages by producing applications that ran up to three times faster than their PL/I counterparts on identical hardware, demonstrating how RISC-inspired optimizations could yield significant speed gains even on traditional CISC processors.
The Cheetah, Panther, and America Initiatives
During the early 1980s, lessons learned from both the 801 and the IBM Advanced Computer Systems culminated in development of the "Cheetah" processor—an experimental 2-way superscalar processor. This concept progressed into "Panther" in 1985 and subsequently into "America" in 1986, which featured a 4-way superscalar design. The America processor comprised three chips: an instruction processor responsible for fetching and decoding instructions; a fixed-point processor sharing execution tasks; and a floating-point processor designed for workloads requiring such capabilities. Although conceived by the original 801 team, final development occurred at IBM’s Austin facility, leading to its deployment within the IBM RS/6000 system. Operating at 25 MHz, this system ranked among the fastest available at that time, outperforming both contemporary RISC architectures and legacy CISC machines by factors of two to three on standard benchmarks.
Building upon the RS/6000 success, IBM concentrated on scaling and refining concepts derived from the 801 architecture efficiently, which ultimately gave rise to the IBM POWER instruction set architecture and its offshoot, PowerPC.
Recognition
John Cocke earned multiple esteemed honors for his groundbreaking contributions to the development of the 801 processor, including:
- 1985: Eckert–Mauchly Award
- 1987: A.M. Turing Award
- 1989: Computer Pioneer Award
- 1991: National Medal of Technology
- 1994: IEEE John von Neumann Medal
- 1994: National Medal of Science
- 2000: Benjamin Franklin Medal
Importantly, Michael J. Flynn identifies the 801 as the inaugural true RISC design.