IBM ROMP
| Industry | Computer hardware, Microprocessors |
|---|---|
| Founded | June 16, 1911 in Endicott, New York, United States |
| Headquarters | Armonk, New York , United States |
| Products | ROMP microprocessor, RT PC, IBM 6152 Academic System |
The ROMP is a reduced instruction set computer (RISC) microprocessor created by IBM during the late 1970s. Also known as the Research OPD Miniprocessor—a name derived from IBM Research and the Office Products Division (OPD)—and sometimes referred to as 032, it was engineered for use in office machinery and compact computing systems. It served as the successor to IBM’s mid-1970s OPD Mini Processor, which was utilized in the IBM Office System/6. The initial ROMP chips were introduced in 1981, with its first commercial application appearing in the IBM RT PC, launched in January 1986. Although originally intended to replace the Intel 8088 processor in IBM’s personal computers, the RT PC was ultimately marketed as a workstation tailored for engineering and scientific tasks. A CMOS adaptation of the ROMP was later incorporated into the coprocessor board of the IBM 6152 Academic System (1988) and certain RT PC variants.
History
The foundation of ROMP’s architecture began in 1977, evolving from IBM Research’s 801 RISC processor. The design aimed at cost efficiency by integrating 16-bit instructions to optimize performance. Initially conceived as a 24-bit processor, it transitioned to a full 32-bit instruction set during its development phase.
By early 1981, the first ROMP chips were completed, marking it as the pioneering industrial RISC microprocessor. It was showcased at the 1984 International Solid-State Circuits Conference and entered mass production in 1985 alongside its memory management unit (MMU) to support manufacturing of the RT PC. The RT PC’s release was postponed due to complex software objectives that involved virtualization capabilities allowing multiple operating systems to run simultaneously—an advanced feature for non-mainframe systems at that time.
The CMOS version of ROMP debuted within the IBM 6152 Academic System and subsequently appeared in select RT PC models. Additionally, IBM Research utilized ROMP in experimental multiprocessor systems such as the Research Parallel Processor Prototype (RP3), which could accommodate up to 512 processors (outlined in 1985), and ACE, a CMOS-based experimental NUMA multiprocessor operational by 1988.
Architecture
ROMP’s design was inspired by the original IBM 801 minicomputer but expanded with a wider 32-bit word size compared to the earlier 24-bit format and incorporated virtual memory. It supported integer sizes of 8, 16, and 32 bits, featured 32-bit addressing, and managed a virtual address space extending to 40 bits. The processor included an instruction pointer along with sixteen general-purpose registers, each 32 bits wide, managed through a set of 118 straightforward instructions varying between 16 and 32 bits.
Its virtual memory architecture employed a segmented address space of 40 bits (equivalent to one terabyte), divided into 4,096 segments of 256 MB each. The MMU constructed the complete 40-bit address by combining a 12-bit segment identifier with 28 bits extracted from ROMP’s native 32-bit virtual address. The segment identifiers were drawn from a set of sixteen stored IDs within the MMU, selected using the four highest-order bits of the calculated address.
Implementation
The ROMP functions as a scalar processor featuring a three-stage pipeline. Instruction processing began with fetching from a 16-byte prefetch buffer; stage one involved decoding and operand retrieval; stage two executed operations; and stage three handled writing results back to registers. To facilitate consecutive execution of dependent instructions without delay, it employed a bypass network alongside carefully scheduled register reads and writes. Most register-to-register instructions completed within a single cycle; out of its total of 118 instructions, eighty-four executed with one-cycle latency.
Complementing ROMP was IBM’s Rosetta chip—an MMU responsible for address translation, including a translation lookaside buffer and store buffering.
Both ROMP and Rosetta were initially fabricated using IBM’s 2 μm NMOS silicon-gate process with two metal layers. The ROMP chip contained approximately 45,000 transistors on a die measuring 7.65×7.65 mm (58.52 mm²), while Rosetta housed around 61,500 transistors on a larger die sized at 9.02×9.02 mm (81.36 mm²). Each chip was enclosed in a ceramic pin grid array package with 135 pins. Subsequently, CMOS variants named ROMP-C and Rosetta-C were developed for enhanced performance and efficiency.