IBM zEC12
| Industry | Computer hardware, Microprocessors |
|---|---|
| Founded | June 16, 1911 in Endicott, New York, United States |
| Headquarters | Armonk, New York , United States |
| Products | zEC12 microprocessor, mainframe computers |
| Website | www |
The zEC12 microprocessor (referred to as zEnterprise EC12 or z12) is an IBM-designed chip intended for the zEnterprise EC12 and BC12 mainframe computer series, officially introduced on August 28, 2012. Produced at IBM’s East Fishkill facility (currently operated by GlobalFoundries), it entered the market in late 2012. IBM asserted it was the fastest microprocessor worldwide at that time, offering approximately a 25% performance increase compared to its predecessor, the z196.
Description
This processor chip spans 597.24 mm2 and incorporates 2.75 billion transistors, which are built using IBM's 32 nm CMOS silicon-on-insulator technology. It achieves a commercial clock frequency of 5.5 GHz, setting a new performance benchmark.
Supporting the CISC z/Architecture, the zEC12 features a superscalar, out-of-order execution pipeline and introduces novel instructions aimed at enhancing transactional processing. Key improvements include advanced branch prediction algorithms, enhanced out-of-order execution capabilities, and a specialized co-processor dedicated to compression and cryptographic tasks. The pipeline consists of 15 to 17 stages; its instruction queue can accommodate up to 40 instructions, while as many as 90 instructions may be concurrently in flight.
Each of the six cores is equipped with private L1 caches (64 KB for instructions and 96 KB for data) and private L2 caches (1 MB each for instructions and data). These cores share a substantial 48 MB L3 eDRAM cache controlled by two on-chip cache controllers. Additionally, there is a shared L1 cache specifically supporting compression and cryptography operations.
Within each core reside six RISC-style execution units: two integer units, two load/store units, one binary floating-point unit, and one decimal floating-point unit. The zEC12 processor is capable of decoding three instructions per cycle while executing up to seven operations simultaneously. Each core also benefits from an individual co-processor accelerator unit, an advancement over the prior generation's shared accelerators.
Integrated on-chip multi-channel DDR3 memory controllers provide RAID-like fault tolerance configurations. The chip further incorporates two GX bus controllers that facilitate connections to host channel adapters and peripheral devices.
The zEC12 includes a 48 MB L3 cache shared across its six cores and symmetric multiprocessing resources. This is augmented by two dedicated Shared Cache (SC) companion chips, each supplying 192 MB of off-die L4 cache memory. Combined, these provide a total of 384 MB L4 cache accessible by all processors within the system. The SC chips are manufactured using the same process technology as the zEC12 and measure 28.4 by 23.9 mm, containing 3.3 billion transistors each.
Multi-chip module
The zEnterprise System EC12 utilizes multi-chip modules (MCMs) that integrate six zEC12 processors alongside two shared cache chips. These components interconnect through high-speed links operating at 40 GB/s. Each individual zEC12 chip has a power consumption near 300 W, with liquid cooling systems rated at 1800 W employed to manage thermal output for the MCMs. Different model configurations adjust core counts by disabling certain fifth and/or sixth cores within processors mounted on the MCM.