Interrupt priority level
| Company type | Concept |
|---|---|
| Industry | Computer science |
The interrupt priority level (IPL) represents a component of the active system interrupt state, defining which interrupt requests are permitted. Hardware implementations of IPL often involve registers within a programmable interrupt controller, whereas software approaches utilize bitmasks or integer values to signify priority.
Overview
An IPL based on integers can be as straightforward as a single binary digit with two states: 0 indicating all interrupts are allowed, and 1 meaning all are blocked, such as in the MOS Technology 6502. More advanced architectures provide a wider spectrum of levels, where each increment grants permission for interrupts of higher precedence while suppressing those at the same or lower tiers.
Priority assignment is crucial for optimizing system throughput alongside interrupt latency. Some interrupts demand rapid handling despite minimal processing, warranting elevated priority status.
Controlling IPL also plays a vital role in coordinating access to kernel data structures. For instance, when a level-3 scheduler interrupt occurs, the IPL is raised to 7 before interacting with scheduler data and subsequently lowered prior to context switching. To preserve synchronization integrity, interrupt handlers are prevented from reducing the IPL below their initial entry level.
The intricacies introduced by Multiprocessor environments are beyond the scope of this discussion.
In many typical UNIX-style systems, only two IPL states are employed: a minimum level where all interrupts are disabled and a maximum level where they are fully enabled.
OpenVMS IPLs
The VAX architecture and VMS operating system utilize 32 distinct priority levels ranging from 0 to 31. External hardware interrupts are managed at levels 16 and above, while levels below 16 are designated for internal software interrupts. Notable priority levels include:
- 31: designated for "power-fail" interrupts.
- 24: assigned to clock interrupts, which take precedence over I/O.
- 20–23: reserved for various I/O devices.
- 8–11: used for fork interrupts that defer lengthy device interrupt processing, analogous to Linux's "bottom halves."
- 7: employed to synchronize access to process scheduler data.
- 4: handles I/O post-processing activities, completing QIO requests.
- 3: triggers process rescheduling; code executed at this level must not assume the current process context.
- 2: synchronizes access to per-process data; at this level, the kernel issues a special kernel AST.
- 0: represents normal execution mode for non-interrupt operations, including user applications.
Alpha hardware inherently supports IPL functionality. When OpenVMS was adapted for the Itanium platform in 2001, its IPL mechanism was emulated through Itanium's hardware capabilities.