Itanium
| Company type | Microprocessor series |
|---|---|
| Industry | Semiconductor |
| Predecessor | IA-64 (Intel Itanium architecture) |
| Founded | June 2001 |
| Founder | Hewlett-Packard, Intel |
| Defunct | July 29, 2021 |
| Fate | Discontinued |
| Headquarters | United States |
Area served | Enterprise servers, high-performance computing |
| Products | 64-bit microprocessors |
Itanium (; ) represents a now-discontinued series of Intel microprocessors built on the Intel Itanium architecture (previously known as IA-64), featuring 64-bit processing capabilities. This architecture originated at Hewlett-Packard (HP) and was co-developed with Intel, with the initial launch occurring in June 2001. The platform was designed primarily for enterprise server environments and high-performance computing applications. Early forecasts predicted that Itanium would supplant the Xeon processor in server markets and eventually replace conventional RISC and complex instruction set computing (CISC) architectures in general-purpose computing.
Despite over ten years of development, Itanium’s initial performance fell short compared to established RISC and CISC CPUs, particularly struggling with emulation of existing x86 software. HP, and later Hewlett Packard Enterprise (HPE), manufactured systems based on Itanium under the Integrity Servers brand, alongside additional vendors. By 2008, Itanium ranked as the fourth most prevalent microprocessor architecture within enterprise-class systems, behind x86-64, Power ISA, and SPARC.
Intel introduced the final Itanium model, codenamed Kittson, to select customers in February 2017, commencing mass distribution by May. This processor remained dedicated to mission-critical servers produced by HPE. In 2019, Intel declared it would cease accepting orders after January 30, 2020, with the last shipments scheduled for July 29, 2021—both milestones were achieved on time.
The Itanium platform’s presence was limited to enterprise server and high-performance computing sectors. Ultimately, its architecture was surpassed by AMD's compatible x86-64 extension, which Intel incorporated into its Xeon processors and AMD into its Opteron line. By 2009, x86-64 processors dominated server sales as well as budget desktops and laptops—market segments where Itanium never competed. Industry analysts attribute Itanium’s decline to its lack of legacy 32-bit support and complexities in software development, whereas AMD64 extensions realized the goal of a unified instruction set architecture.
Origins: 1989–1994
In 1989, HP initiated research aimed at creating an architecture that would overcome the limitations inherent in reduced instruction set computer (RISC) designs, focusing on handling multiple instructions per cycle alongside dynamic dependency analysis and precise exception management. To achieve this, HP recruited leading figures in very long instruction word (VLIW) technology, Bob Rau and Josh Fisher, to architect a novel design. Departing from traditional VLIW approaches, HP’s concept—later termed Explicitly Parallel Instruction Computing (EPIC)—incorporated template bits to denote instruction independence, predication to minimize branching operations, and comprehensive interlocking mechanisms to avoid delay slots. EPIC enabled hardware to autonomously assign execution units and schedule timing, thereby improving flexibility and operational efficiency. HP intended to apply EPIC within PA-WideWord, the successor ISA to their existing PA-RISC. Internal benchmarks in 1993 demonstrated simulated EPIC performance exceeding that of conventional RISC designs by more than twofold.
Meanwhile, Intel was investigating enhancements to instruction set architectures. Its 1989 i860 processor supported explicit parallelism modes and featured an exposed floating-point pipeline; however, it failed commercially due to inadequate compiler technology. Intel’s efforts to develop a 64-bit extension for x86 processors faced obstacles until HP approached Intel in November 1993 proposing collaboration on a new architecture.
At that time, Intel was working on the P7 processor aimed at extending x86 to 64 bits but encountered challenges regarding economic viability. Impressed by HP’s PA-WideWord presentation, Intel engineers including John Crawford—who became Merced’s chief architect in 1994—joined forces with HP. The two companies formed a joint team exchanging confidential research and agreed to base their forthcoming architecture on PA-WideWord combined with HP Labs’ experimental PlayDoh project. Intel subsequently abandoned its original P7 design in favor of this joint initiative.
In June 1994, Intel and HP officially announced their partnership to create a new ISA integrating Wide Word and VLIW principles. Intel suggested some features might appear in early P7 chips but indicated the complete architecture would be introduced later. By early 1996, Intel disclosed the project codename as Merced.
Recognizing the rising costs associated with proprietary microprocessor development, HP chose to collaborate with Intel in 1994 on IA-64—a derivative of EPIC. Intel invested substantial resources anticipating IA-64 processors would become widely adopted across enterprise system manufacturers. The partnership targeted delivering Merced processors by 1998.
Design and delays: 1994–2001
The Merced project involved a team of approximately 500 individuals, many of whom were recent graduates, a fact Intel later recognized as a factor in the team's relative inexperience. Crawford from Intel served as the lead architect, with Huck from HP acting as his deputy. Initial conflicts arose concerning hardware design choices, particularly regarding floating-point units; HP’s perspective gained prominence following the Pentium FDIV flaw. When Merced’s floorplan was finalized around mid-1996, its excessive size necessitated compromises in complexity and performance, including reducing the L2 cache to 96 KB—a stark contrast to the 2 MB cache found on the Pentium III Xeon MP. To meet size constraints, the manufacturing process was shifted from 250 nm down to 180 nm. Subsequent attempts to accelerate critical timing paths introduced additional hurdles. The chip was taped out on July 4, 1999, with the first fully functional test silicon produced by August of that year.
Performance shortcomings and schedule slippages lowered expectations for Merced, redirecting attention toward the second-generation Itanium design led by HP, known as McKinley. Transitioning to the 180 nm process delayed Merced’s release until late 1999. Prior to EPIC’s public introduction in October 1997, industry analysts anticipated that competitive performance levels would only be achievable by McKinley around 2001. Intel’s Fred Pollack asserted that McKinley would deliver twice Merced’s performance while utilizing the same 180 nm technology but conceded that Merced’s x86 compatibility lagged behind the fastest x86 processors available at the time. Intel forecasted that IA-64 would have minimal impact on consumer markets for a period of five to ten years.
HP began work on McKinley in 1996 to exert greater control over development and circumvent issues encountered with Merced, setting definitive objectives by 1997. By mid-1998, Merced’s launch had slipped to mid-2000, prompting skepticism about its market viability since McKinley promised significantly enhanced performance shortly thereafter. The prevailing sentiment became one of waiting for McKinley, with HP extending its PA-RISC processor line through the PA-8900, which was expected to reach speeds of up to 1.2 GHz by 2003.
By early 1999, volume production of Merced was projected only for 2001, with limited customer adoption anticipated as many awaited McKinley’s arrival. Delays persisted into mid-1999; consensus among analysts held that Merced would primarily serve debugging and software development needs. Intel set an initial price point around $5000. In August 1999, HP advised certain clients to bypass Merced in favor of McKinley. By July 2000, HP described early Itanium systems as niche offerings unlikely to be adopted within data centers for several years; Itanium-based systems were not expected to outsell PA-RISC products until approximately 2005.
Intel announced additional postponements due to necessary bug fixes; pilot systems were shipped late in 2000 while general availability was deferred until early 2001. Most server manufacturers postponed research and development investments in Merced platforms, instead opting for Intel-designed motherboards or servers. To foster ecosystem growth, Intel distributed roughly 15,000 Itanium processors across about 5,000 systems to developers by mid-2000. In March 2001, Intel confirmed shipments would commence in the second quarter with broader deployment later that year but acknowledged many customers would still prefer to wait for McKinley.
Expectations
Throughout its development phase, Intel, HP, and industry analysts anticipated that IA-64 would initially dominate the market for 64-bit servers and workstations before expanding into lower-tier servers and eventually replacing Xeon processors and entering the personal computer space. Intel envisioned IA-64 supplanting both RISC and CISC architectures for general-purpose computing applications while maintaining that x86 compatibility would remain relevant "for the foreseeable future." Between 1997 and 1998, Intel CEO Andy Grove projected that Itanium would not penetrate desktop markets for at least four to five years after launch, with widespread desktop adoption unlikely within a decade. However, Itanium was expected to capture approximately 70% of the 64-bit server segment by 2002.
By 1998, Itanium’s focus on premium market segments attracted criticism due to potential threats from competitors targeting lower-end markets. Nonetheless, skepticism within the industry was often muted because of concerns about Intel's dominant position and potential repercussions. Companies such as Compaq and Silicon Graphics ceased further development of DEC Alpha and MIPS architectures respectively in favor of transitioning their platforms to IA-64.
Several operating systems were ported onto IA-64 architecture including Microsoft Windows, OpenVMS, Linux, HP-UX, Solaris, Tru64 UNIX, and Project Monterey (Monterey/64). The latter three were ultimately canceled prior to commercial release. By 1997, IA-64’s architectural intricacies and compiler challenges contributed significantly to delays in delivering Merced.
Intel officially designated the processor as Itanium on October 4, 1999. Within hours of this announcement, the nickname Itanic emerged on Usenet forums—a play on words referencing RMS Titanic, famously deemed "unsinkable" before sinking during its maiden voyage in 1912. This pejorative nickname quickly gained traction within media outlets such as The Register, symbolizing skepticism that the considerable financial investment and early enthusiasm surrounding Itanium might soon give way to rapid decline.
Itanium (Merced): 2001
Following the distribution of 40,000 sample chips to partners, Intel officially introduced the Itanium processor on May 29, 2001. The first OEM systems incorporating Itanium, produced by HP, IBM, and Dell, began shipping in June of the same year. Nevertheless, Itanium's performance did not surpass that of existing RISC and CISC processors. The processor was designed to serve both lower-tier x86-based servers—mainly those with up to four CPUs—and higher-end markets competing against IBM POWER and Sun SPARC architectures. Intel subsequently refocused Itanium toward high-performance computing and enterprise segments, aiming to emulate the widespread success achieved by x86 processors.
Initially, this processor replaced HP’s PA-RISC, Compaq’s Alpha, and SGI’s MIPS platforms; IBM also implemented an Itanium-powered supercomputer. Despite these deployments, IBM’s POWER and Sun’s SPARC systems maintained their market strength, while 32-bit x86 processors continued to grow within enterprise environments due to their extensive installed base.
Sales of Merced-based systems remained limited to a few thousand units because of subpar performance, elevated costs, and a scarcity of compatible software. To mitigate software availability issues, Intel distributed numerous early systems to independent software vendors to stimulate development efforts. A year later, HP and Intel released the successor Itanium 2 processor. Most microarchitectural elements from Merced—such as the 16+16 KB L1 cache and the 6-wide instruction decode capability—were omitted in later Itanium iterations.
Itanium 2 (McKinley and Madison): 2002–2006
The Itanium 2 processor debuted in July 2002 with a focus on enterprise server applications rather than broad high-performance computing markets. The initial variant, known as McKinley, was co-designed by HP and Intel under the leadership of HP’s Fort Collins team. This generation tackled the original Itanium’s performance shortcomings by reducing cache latency by half and doubling bandwidth across all three cache levels; notably, the L2 cache size increased from 96 KB to 256 KB. Floating-point operations bypassed the L1 cache to exploit L2's enhanced bandwidth typical for such workloads. The integrated L3 cache featured triple associativity and twice the bus width compared to its predecessor. Additionally, McKinley expanded the number of instructions per VLIW bundle and attained a 25% higher clock frequency while utilizing fewer pipeline stages.
The McKinley chip contained 221 million transistors (25 million dedicated to logic and 181 million for L3 cache), measured 19.5 mm by 21.6 mm (421 mm²), and was manufactured using a 180 nm CMOS technology. In May 2003, a critical-path erratum was identified that could lead to system crashes; however, this issue could be circumvented by operating at a reduced frequency of 800 MHz.
Following AMD's introduction of the Opteron processor in 2003 with its AMD64 architecture—which quickly gained traction in enterprise settings due to its backward compatibility with x86—Intel adjusted its approach. Under Microsoft’s influence, Intel incorporated AMD’s x86-64 instruction set architecture into its Xeon processors in 2004, thereby establishing a new industry standard.
In 2003, Intel broadened the Itanium 2 family with the Madison variant, which offered clock speeds up to 1.5 GHz and an L3 cache size of 6 MB. The Madison 9M model launched in late 2004 increased L3 cache capacity to 9 MB and reached frequencies up to 1.67 GHz by mid-2005. Both chips were fabricated using a 130 nm process technology and formed the basis for subsequent Itanium products until the release of Montecito in July 2006. Related variants included Deerfield, a low-power version of Madison, and Fanwood, which targeted lower-end one- or two-socket servers based on Madison 9M.
In November 2005, leading manufacturers of Itanium servers collaborated with Intel and software vendors to establish the Itanium Solutions Alliance. This consortium aimed to promote the architecture and expedite software porting efforts. The Alliance pledged an investment totaling $10 billion by the end of the decade to foster growth within the Itanium ecosystem.
Itanium 2 9000 and Itanium 9100: 2006 and 2007
To counter IBM's achievement with the dual-core POWER4, Intel postponed the debut of its initial 90 nm Itanium chip, known as Montecito, to 2005. This delay allowed integration of dual-core capabilities by combining it with the Chivano initiative. By September 2004, Intel had showcased a functional Montecito system, emphasizing hyper-threading technology that improved performance by 10 to 20 percent and aimed for clock speeds reaching 2 GHz. Despite subsequent postponements and a reduction in clock frequency to 1.6 GHz, Intel officially released Montecito on July 18, 2006, branding it as the Itanium 2 9000 series. This processor featured dual cores with switch-on-event multithreading and divided L2 caches (256 KB plus 1 MB), nearly doubling performance while lowering power consumption by approximately one-fifth. With a die size of 596 mm² housing 1.72 billion transistors, it was the largest microprocessor at that time. Although designed to include Foxton Technology—an advanced frequency control mechanism—this functionality was not commercially activated due to unresolved validation challenges.
In November 2007, Intel launched the Itanium 9100 family, internally called Montvale, which marked the end of the "Itanium 2" naming convention. Initially intended for a 65 nm fabrication process, Montvale was an enhancement of Montecito featuring demand-based switching akin to Enhanced Intel SpeedStep Technology (EIST), increased front-side bus speeds up to 667 MT/s, and added core-level lockstep for improved fault tolerance. Both Montecito and Montvale represented the last Itanium processors significantly influenced by Hewlett-Packard’s engineering team in Fort Collins before their transition under Intel's full control.
Itanium 9300 (Tukwila): 2010
The first multi-core iteration of Itanium, initially codenamed Tanglewood but renamed Tukwila in late 2003 due to trademark conflicts, was developed by the DEC Alpha group as Montecito’s successor with a focus on substantially enhanced performance. Early designs envisioned up to eight cores with multithreading support, targeting performance improvements exceeding sevenfold compared to Madison. However, by early 2005, the architectural strategy shifted toward fewer cores prioritizing strong single-thread throughput and better scalability in multiprocessor configurations.
Intel disclosed in March 2005 that Tukwila would incorporate four cores and replace the conventional Itanium bus architecture with the Common System Interface (CSI), which was also planned for a now-canceled Xeon processor named Whitefield. After several delays, Tukwila finally launched on February 8, 2010.
The Itanium 9300 series (Tukwila) was fabricated using a 65 nm process and featured between two and four cores, up to 24 MB of integrated cache, Hyper-Threading capabilities, and built-in memory controllers. Its design replaced the traditional bus structure with Intel QuickPath Interconnect (QPI), achieving peak inter-processor bandwidth of 96 GB/s alongside memory bandwidth reaching 34 GB/s. QPI facilitated direct connections between processors and I/O hubs while aligning Tukwila’s platform architecture with Intel’s Nehalem-based Xeon processors.
Tukwila also integrated two memory controllers connected to Scalable Memory Buffers that supported multiple DDR3 DIMMs, similar to the Nehalem-based Xeon "Beckton" processor, thereby enhancing memory capacity and throughput critical for enterprise workloads.
HP versus Oracle
During the 2012 legal dispute Hewlett-Packard Co. v. Oracle Corp., court records disclosed that HP compensated Intel approximately $440 million in 2008 to sustain the manufacturing and enhancement of Itanium microprocessors from 2009 through 2014. Subsequently, in 2010, HP entered into an additional agreement worth $250 million, obligating Intel to supply Itanium CPUs to HP until 2017. These contracts involved HP funding the chips while Intel introduced successive processors—Tukwila, Poulson, Kittson, and Kittson+—to progressively elevate platform capabilities.
Itanium 9500 (Poulson): Released 2012
Intel initially mentioned the Poulson processor on March 1, 2005, and by June 2007 announced plans to manufacture it using a 32 nm fabrication process. This approach bypassed the intermediate 45 nm node to compensate for delays that had caused Itanium to lag behind competitors utilizing more advanced process technologies.
At the ISSCC conference in 2011, Intel presented Poulson as a high-performance Itanium CPU with 3.1 billion transistors and a 12-wide instruction issue width, tailored for critical server applications. Analyst David Kanter highlighted Poulson’s new microarchitecture incorporating advanced multithreading capabilities with support for up to two threads per core, enhancing both single-threaded and multithreaded workloads. Further details at the Hot Chips symposium emphasized improvements such as robust multithreading, enhanced fault tolerance via Intel Instruction Replay RAS, and novel instructions designed to optimize virtualization and parallel processing.
The Itanium 9500 line was officially launched on November 8, 2012, succeeding the Tukwila generation. Poulson featured eight cores with a 12-wide issue pipeline and improved multithreading functionality. Its unified L3 cache totaled 32 MB shared among all cores, while each core contained a dedicated 6 MB L2 cache divided into 512 KB for instructions and 256 KB for data. The die area measured 544 mm², notably smaller than Tukwila’s 698.75 mm².
Intel’s Product Change Notification outlined four distinct Itanium 9500 models later detailed in Intel’s Material Declaration Data Sheets and reference manuals:
| Processor model | Clock speed | Cache size |
|---|---|---|
| 9520 | 1.73 GHz | 20 MB |
| 9540 | 2.13 GHz | 24 MB |
| 9550 | 2.40 GHz | 32 MB |
| 9560 | 2.53 GHz | 32 MB |
Itanium 9700 (Kittson): Released 2017
Initially intended as a next-generation Itanium processor fabricated on a 22 nm process and utilizing the LGA2011 socket compatible with Xeon CPUs, Kittson's design was revised by January 2013. Intel confirmed that Kittson would instead employ the existing 32 nm process and maintain compatibility with the LGA1248 socket used by Poulson, marking an effective cessation of significant new development for Itanium.
In April 2015, Intel reiterated ongoing efforts on Kittson but signaled minimal research investment, projecting only a modest performance improvement of approximately 20%. Concurrently, Intel’s multicore Xeon E7 platform increasingly supplanted Itanium within the company’s strategic roadmap. Hewlett-Packard, the primary purchaser of Itanium processors, transitioned its focus towards x86-based Superdome and NonStop server lines, treating Itanium systems as legacy technology.
The Itanium 9700 series was officially introduced on May 11, 2017. Kittson offered no architectural advancements over Poulson and was architecturally identical to the preceding 9500 series; its main distinction was a slight clock speed increase of up to 133 MHz. Intel declared the 9700 lineup as the concluding generation of Itanium processors.
The Itanium 9700 series comprises these models:
| Processor model | Core count | Thread count | Clock speed | Cache size |
|---|---|---|---|---|
| 9720 | 4 | 8 | 1.73 GHz | 20 MB |
| 9740 | 8 | 16 | 2.13 GHz | 24 MB |
| 9750 | 4 | 8 | 2.53 GHz | 32 MB |
| 9760 | 8 | 16 | 2.66 GHz | 32 MB |
In contrast to Intel's Xeon server processors, Itanium never achieved high production volumes. Although Intel has not publicly disclosed exact manufacturing figures, industry estimates suggested that approximately 200,000 Itanium chips were produced annually in 2007.
Gartner Inc. reported that around 55,000 Itanium-based servers were sold by all vendors during 2007, whereas sales of RISC servers reached 417,000 units and x86 servers totaled 8.4 million. IDC indicated that from 2001 through 2007, about 184,000 systems utilizing Itanium processors were shipped. In the combined market for POWER, SPARC, and Itanium platforms, IDC recorded that in the second quarter of 2008, POWER held a revenue share of 42%, SPARC accounted for 32%, and Itanium represented 26%. HP dominated the Itanium segment, generating roughly 80% of total revenue in 2007 and capturing 95% of sales in 2008. By the end of 2008, HP's annual Itanium system revenue reached $4.4 billion but decreased to $3.5 billion by the close of 2009 amid a general decline in UNIX revenues and a concurrent 14% rise in x86-64 server sales.
IDC predicted in December 2012 that shipments of Itanium servers would remain stable at about 26,000 units per year through 2016—reflecting a drop exceeding half compared to figures from 2008.
Systems
| Vendor | Final product | |||
|---|---|---|---|---|
| name | start | end | model | CPU count |
| HP/HPE | 2001 | 2021 | Integrity | 1–256 |
| Compaq | 2001 | 2002 | ProLiant 590 | 1–4 |
| IBM | 2001 | 2005 | System x455 | 1–16 |
| Dell | 2001 | PowerEdge 7250 | 1–4 | |
| Hitachi | 2001 | 2008 | BladeSymphony 1000 |
1–8 |
| Unisys | 2002 | 2009 | ES7000/one | 1–32 |
| SGI | 2001 | 2011 | Altix 4000 | 1–2048 |
| Fujitsu | 2005 | PRIMEQUEST | 1–32 | |
| Bull | 2002 | pre-2015 | NovaScale 9410 | 1–32 |
| NEC | 2002 | 2012 | nx7700i | 1–256 |
| Inspur | 2010 | pre-2015 | TS10000 | 2–1024 |
| Huawei | 2012 | pre-2015 | Template:Dunno | Template:Dunno |
By the year 2006, HP was responsible for manufacturing at least four-fifths of all Itanium systems and reported sales of roughly 7,200 units just during the first quarter. The majority of these systems were enterprise-grade servers or extensive technical computing platforms with average prices surpassing $200,000 and generally equipped with eight or more Itanium processors.
By the year 2012, only a handful of companies continued to offer Itanium-based systems: HP, Groupe Bull, NEC, Inspur, and Huawei. Additionally, Intel supplied chassis components for system integrators assembling Itanium servers.
By the time it reached 2015, HP remained the exclusive producer of systems powered by Itanium processors. After HP's corporate division later that year, the Itanium product line (marketed as Integrity) transitioned under Hewlett Packard Enterprise (HPE), which launched a significant upgrade in 2017 featuring Integrity i6 servers alongside HP-UX 11i version 3 Update 16. HPE's supported operating systems include various releases such as Windows Server up to version 2008 R2, Linux, OpenVMS, and NonStop. Importantly, the Itanium architecture is immune to vulnerabilities related to the Spectre and Meltdown exploits.
Chipsets
Prior to the introduction of the 9300-series (Tukwila), chipsets played a crucial role in linking processors to main memory and input/output devices through the front-side bus. Two principal bus generations were utilized: the initial Itanium processor system bus operating at 64-bit, 133 MHz DDR speeds, and the upgraded 128-bit 200 MHz DDR Itanium 2 processor system bus, which eventually advanced to 533 and 667 MT/s rates. A single bus could accommodate up to four CPUs, though speeds exceeding 400 MT/s were restricted to two processors per bus. Because no chipset supported more than four sockets, high-performance servers required multiple chipsets interconnected.
The "Tukwila" Itanium was engineered to share a unified chipset platform with Intel's Xeon processor EX, aiming to simplify development efforts and lower costs for OEMs manufacturing both Itanium- and Xeon-based systems. Nevertheless, this integration was postponed for reassessment in 2013.
Before the advent of on-chip memory controllers and QPI, manufacturers of enterprise servers distinguished their products by designing proprietary chipsets that connected processors with memory, interconnects, and peripheral devices. This approach was particularly justified in high-end servers featuring 16 or more sockets, where investing tens of millions of dollars in chipset development represented a significant commitment to the Itanium platform.
Neither Intel nor IBM created Itanium 2 chipsets compatible with newer technologies such as DDR2 or PCI Express. Until "Tukwila" transitioned away from front-side bus architecture, major Itanium server vendors—including HP, Fujitsu, SGI, NEC, and Hitachi—were responsible for chipset production.
Intel
Intel’s first-generation Itanium systems exclusively utilized the 460GX chipset, composed of ten separate chips. This chipset supported up to four CPUs and 64 GB of memory at a bandwidth of 4.2 GB/s—twice the throughput of the system bus. It incorporated distinct chips for address and data handling, an AGP X4 graphics interface, two PCI buses operating at 64-bit and 66 MHz, as well as configurable PCI options.
For Itanium 2 platforms, many vendors adopted Intel’s E8870 chipset, which supported up to 128 GB of DDR SDRAM at 6.4 GB/s. Initially designed for Rambus RDRAM memory, Intel integrated four DDR SDRAM-to-RDRAM converter chips following RDRAM’s market failure, despite earlier concerns about performance degradation with similar converters in Pentium III chipsets. The E8870 includes eight PCI-X buses running at 133 MHz (though aggregate throughput is limited to 4.2 GB/s due to bottlenecks) and an ICH4 hub offering six USB 2.0 ports.
Linking two E8870 chipsets is possible via E8870SP Scalability Port Switches equipped with a 1MB snoop filter each. This configuration enables an eight-socket system with doubled memory and PCI-X capabilities but retains only a single ICH4 hub. There were intentions to scale this architecture up to sixteen sockets.
In 2004, Intel announced the Bayshore chipset for Itanium systems intended to support PCI-e and DDR2 memory; however, this project was canceled within the same year.
Hewlett-Packard
HP engineered four distinct Itanium 2 chipsets: zx1, sx1000, zx2, and sx2000. Each supports up to four sockets per chipset; the sx1000 and sx2000 models allow interconnecting as many as sixteen chipsets for a total of 64 sockets. The zx1 chipset was developed alongside Itanium 2 and booted the first Itanium 2 processor in February 2001. By 2004 it was the earliest chipset supporting a front-side bus speed of 533 MT/s. Its basic two-chip configuration provides four channels of DDR-266 memory delivering an aggregate bandwidth of 8.5 GB/s with a maximum capacity of 32 GB across twelve DIMM slots. When combined with memory expander boards, bandwidth increases to 12.8 GB/s and capacity reaches up to 128 GB; however, this comes at a cost of approximately a 25 ns increase in latency. Eight independent links supply up to 4 GB/s bandwidth to PCI-X buses and other peripheral devices.
The high-performance sx1000 chipset debuted mid-2003 alongside HP’s Integrity Superdome server platform. It features two independent front-side buses—each capable of supporting two sockets—providing combined processor-to-chipset bandwidth of 12.8 GB/s. The chipset supports HP-designed memory modules totaling up to 64 GB at a throughput of 16 GB/s via four data-only memory buffer links. The system board unit—referred to as a cell—can be interconnected with another cell for an eight-socket configuration or expanded up to sixteen cells (64 sockets) using crossbar switches that deliver a bisection bandwidth of 32 GB/s. Cache coherence is maintained through in-memory directory structures; local memory latency is approximately 241 ns while remote NUMA latency measures around 463 ns. Despite having PCI-X buses capable of aggregating up to 8 GB/s, I/O bandwidth per cell is capped at roughly 2 GB/s.
In March 2006, HP introduced the sx2000 chipset as a successor to the sx1000. This chipset operates dual front-side buses at speeds of 533 MT/s and supports custom DDR2 memory configurations up to 128 GB with peak bandwidth reaching 17 GB/s. Inter-chipset communication is facilitated through three serial links connecting sets of crossbar switches delivering a combined bandwidth of 25.5 GB/s—improving parallelism over previous designs. The architecture scales up to a maximum of sixty-four sockets achieving sustainable bisection bandwidths near 72 GB/s. The sx2000 connects with its I/O module via a serial link providing peak throughput of approximately 8.5 GB/s; this module supports configurations including twelve PCI-X buses running at up to 266 MHz or mixed setups comprising six PCI-X and six PCIe version 1.1 ×8 slots. Notably, this was the final chipset compatible with HP’s PA-RISC PA-8900 processors.
HP’s zx2-based server platforms launched in September 2006 utilize the zx2 chipset, which supports front-side bus speeds up to 667 MT/s when operating two CPUs or maintains speeds of 533 MT/s with four CPUs installed. The zx2 connects directly to DDR2 memory modules supporting up to 32 GB at bandwidths around 14.2 GB/s or can interface through expander boards increasing capacity up to an impressive maximum of 384 GB at bandwidths near 17 GB/s; latencies range between approximately 60 and 78 ns depending on configuration. Eight independent links provide total I/O bandwidth around 9.8 GB/s supporting adapters such as PCIe ×8 and PCI-X running at frequencies up to 266 MHz.
Additional Chipsets
In May 2003, IBM introduced the XA-64 chipset designed for Itanium 2 processors, evolving from earlier XA-32 chipsets originally developed for Xeon. By the time the third generation of XA-32 arrived, IBM had phased out its Itanium product line. The XA-64 chipset accommodated up to 56 GB of DDR SDRAM across 28 slots, delivering a theoretical bandwidth of 6.4 GB/s. However, practical limitations constrained CPU bandwidth to 3.2 GB/s and peripheral devices to 2 GB/s, resulting in an aggregate throughput of 5.2 GB/s. To alleviate CPU memory access bottlenecks, an external 64 MB DRAM L4 cache was implemented, which also functioned as a snoop filter in configurations involving multiple chipsets. The total bandwidth available from four PCI-X buses and other I/O channels was restricted to 2 GB/s per chipset. Systems could be configured with either two or four chipsets, supporting eight or sixteen processor sockets respectively.
SGI employed the SHUB (Super-Hub) chipset within its Altix supercomputer line, enabling support for dual Itanium 2 sockets. The first generation SHUB provided DDR memory access via four channels, reaching up to 12.8 GB/s bandwidth and supporting a maximum of 32 GB across sixteen DIMM slots. Connectivity included a 2.4 GB/s XIO interface linked to expansion modules featuring up to six 64-bit 133 MHz PCI-X buses. Multiple SHUBs were interconnected through dual planes of 6.4 GB/s NUMAlink4 links, facilitating cache-coherent systems scaling up to 512 sockets. To reduce latency and minimize memory bandwidth consumption, a dedicated cache stored the in-memory coherence directory. Local memory access latency measured approximately 132 ns, with each NUMAlink4 router introducing an additional delay of around 50 ns. I/O modules equipped with four PCI-X buses connected directly into the NUMAlink4 fabric.
The second iteration, SHUB 2.0, enhanced capabilities by supporting up to 48 GB of DDR2 memory, a front-side bus operating at 667 MT/s, and PCI Express-based I/O modules. This chipset supports only four local hardware threads; consequently, when two dual-core CPUs are installed per chipset, Hyper-Threading technology must be disabled.
Unix
- HP-UX version 11 (with support maintained through 2025)
BSD
- NetBSD (classified as a tier II port; an ongoing project aimed at porting NetBSD to Itanium architecture without an official release)
- FreeBSD (support discontinued as of October 31, 2018)
Linux
The Trillian Project represented a collaborative industry initiative launched in May 1999 to port the Linux kernel to the Itanium platform, targeting an initial code release by early 2000. By late 1999, the consortium comprised organizations such as Caldera Systems, CERN, Cygnus Solutions, Hewlett-Packard, IBM, Intel, Red Hat, SGI, SuSE, TurboLinux, and VA Linux Systems. The project successfully delivered code in February 2000, which was integrated into the mainline Linux kernel more than a year prior to the commercial debut of the first Itanium processor. Key factors enabling this accomplishment included:
- The existing support for Itanium architecture within the open source GCC.
- The availability of a free open source simulator emulating Itanium processors.
Following Project Trillian’s success, all major Itanium system vendors—including HP, IBM, Dell, SGI, Fujitsu, Unisys, Hitachi, and Groupe Bull—embraced Linux as their operating system of choice. Except for HP systems, Linux often serves as the primary or exclusive OS on Itanium platforms. Ongoing open source Linux development for Itanium has been coordinated under the auspices of the Gelato initiative.
Distribution support
Fedora Linux introduced Itanium compatibility in 2005, coinciding with Novell incorporating support for SUSE Linux. In 2007, CentOS launched a release that included Itanium support.
Prominent distributions that have provided Itanium compatibility are:
- Debian (official support ended with Debian 8; unofficial availability continued through Debian Ports until June 2024)
- EPIC Slack, an unofficial port of Slackware, has supported IA-64 since May 2024
- Gentoo Linux (support maintained until August 2024)
- Red Hat Enterprise Linux (Itanium support persisted up to RHEL 5, ending in 2017; no support from RHEL 6 onward)
- SUSE Linux 11 (Itanium support lasted until 2019; other architectures supported until 2022)
- T2 SDE includes Itanium compatibility within its IA-64 port
These distributions illustrate a continuing, albeit diminishing, dedication by both commercial entities and the community toward the Itanium ecosystem.
Deprecation
Red Hat discontinued Itanium support starting with Enterprise Linux 6 in 2009. Similarly, Ubuntu ceased Itanium compatibility with version 10.10. In 2021, Linus Torvalds declared the Itanium codebase orphaned, highlighting that HPE had stopped accepting new orders for Itanium hardware and Intel had done so a year prior. Although Intel officially shipped processors until July 29, 2021, actual new orders were improbable. Torvalds summarized the situation succinctly: "It's dead, Jim."
Linux kernel support for Itanium was removed in version 6.7, with any ongoing maintenance now performed outside the mainline tree.
Microsoft Windows
- Windows XP 64-Bit Edition (support ended June 30, 2005)
- Windows Server 2003 (support ended July 14, 2015)
- Windows Server 2008 (support ended January 14, 2020; paid Extended Security Updates were not offered for Itanium)
- Windows Server 2008 R2 (support ended January 14, 2020; last Windows release compatible with Itanium processors; paid Extended Security Updates unavailable for Itanium)
OpenVMS
In 2001, Compaq announced plans to port OpenVMS to the Itanium platform, leading to V8.x versions that supported both Itanium-based HPE Integrity Servers and legacy DEC Alpha systems. Ownership transitioned from Compaq to HP in 2001 and later to VMS Software Inc. (VSI) in 2014. Significant releases include:
- V8.0 (2003) – The initial pre-production OpenVMS version for Itanium distributed outside HP.
- V8.2 (2005) – The first production-ready OpenVMS release on Itanium.
- V8.4 (2010) – The final HP-supported OpenVMS edition; official support concluded on December 31, 2020.
- V8.4-2L3 (2021) – The last VSI-supported OpenVMS release for Itanium; support extends through December 31, 2035.
Support for Itanium was discontinued with OpenVMS V9.x releases, which are exclusively designed for x86-64 architectures.
NonStop OS
NonStop OS underwent a transition from MIPS hardware to the Itanium platform in 2005 and later moved to x86-64 in 2015. Sales of NonStop systems based on Itanium ceased in 2020, while support continues until 2025.
Compiler
Following Intel’s announcement of phasing out the platform, the GNU Compiler Collection removed IA-64 support starting with GCC version 10. Likewise, LLVM’s Clang compiler discontinued Itanium compatibility as of version 2.6.
Virtualization and Emulation
HP provides virtualization solutions for Itanium under the name Integrity Virtual Machines.
Prior to IBM's 2009 acquisition of QuickTransit, dynamic binary translation technology allowed execution of IRIX/MIPS and Solaris/SPARC applications on Linux/Itanium platforms. HP also engineered emulation capabilities to support PA-RISC/HP-UX applications on Itanium running HP-UX, easing the transition for PA-RISC users. Furthermore, Itanium CPUs are capable of operating the mainframe GCOS from Groupe Bull as well as various x86 operating systems through instruction set simulation.
Competition
The Itanium architecture was designed primarily for the enterprise server and high-performance computing (HPC) sectors. Its main rivals in these markets included Oracle's and Fujitsu's SPARC processors alongside IBM's Power microprocessors. However, in terms of unit volume, Itanium mainly competed with x86-64 processors such as Intel's Xeon and AMD's Opteron. Since 2009, x86-64 processors have dominated server shipments.
In 2005, Itanium-based systems accounted for roughly 14% of HPC revenue, but this figure diminished as the industry increasingly adopted x86-64 clustered architectures.
An October 2008 analysis by Gartner regarding the Tukwila processor highlighted that "the future roadmap for Itanium appears as robust as those of RISC competitors like Power or SPARC."
Supercomputers and High-Performance Computing
An Itanium-powered system made its initial appearance on the TOP500 supercomputer list in November 2001. The highest ranking attained by an Itanium 2 machine was No. 2 in June 2004 when the Thunder system at Lawrence Livermore National Laboratory achieved 19.94 Teraflops. Later that year, in November 2004, the Columbia supercomputer also secured the No. 2 spot with a performance of 51.8 Teraflops. From that point until June 2007, there was consistently at least one Itanium-based system within the top ten.
The peak number of Itanium systems listed on the TOP500 was 84 units (16.8%) in November 2004. By June 2012, only a single Itanium system remained on the list (0.2%), with none appearing after November 2012.
Released Processors
The development of the Itanium processor family saw considerable advancements over time. Merced acted as a proof-of-concept chip, while McKinley enhanced memory hierarchy to bolster competitiveness. Madison transitioned to a 130 nm fabrication process and expanded cache sizes to alleviate performance constraints. Montecito introduced a dual-core architecture built on a 90 nm process, improving efficiency per watt consumed. Montvale incorporated core-level lockstep functionality, demand-based switching, and increased front-side bus speeds up to 667 MHz.
| Codename | Process | Release Date | Clock Speed | L2 Cache/ per Core |
L3 Cache/ per Processor |
Bus | Dies/ Device |
Cores/ Die |
TDP/ Device |
Remarks |
|---|---|---|---|---|---|---|---|---|---|---|
| Itanium | ||||||||||
| Merced | 180 nm | 2001-05-29 | 733 MHz | 96 KB | 1 MB
2 MB |
266 MHz | 1 | 1 | 116 W | Supports optional off-die L3 cache of 2 or 4 MB |
| 800 MHz | 116 W | Supports optional off-die L3 cache of 2 or 4 MB | ||||||||
| Itanium 2 | ||||||||||
| McKinley | 180 nm | 2002-07-08 | 900 MHz | 256 KB | 1.5 MB | 400 MHz | 1 | 1 | 90 W | Hardware branch prediction enhancements |
| 1 GHz | 100 W | |||||||||
| 3 MB | ||||||||||
| Madison | 130 nm | 2003-06-30 | 1.3 GHz | 3 MB | 97 W | |||||
| 1.4 GHz | 4 MB | 91 W | ||||||||
| 1.5 GHz | 6 MB | 107 W | ||||||||
| 2003-09-08 | 1.4 GHz | 1.5 MB | 91 W | |||||||
| 2004-04-13 | 3 MB | |||||||||
| 1.6 GHz | 99 W | |||||||||
| Deerfield | 2003-09-08 | 1.0 GHz | 1.5 MB | 55 W | Low voltage variant | |||||
| Hondo | 2004-06 | 1.1 GHz | 4 MB | 170 W | HP product featuring a large 32 MB L4 cache | |||||
| Fanwood | 2004-11-08 | 1.3 GHz | 3 MB | 62 W | Low voltage design | |||||
| 1.6 GHz | 99 W | |||||||||
| 533 MHz | ||||||||||
| Madison 9M | 1.5 GHz | 4 MB | 400 MHz | 122 W | ||||||
| 1.6 GHz | 6 MB | |||||||||
| 9 MB | ||||||||||
| 2005-07-05 | 1.67 GHz | 6 MB | 667 MHz | |||||||
| 9 MB | ||||||||||
| Itanium 2 9000 series | ||||||||||
| Montecito | 90 nm | 2006-07-18 | 1.4–1.6 GHz | 256 KB (D)+1 MB (I) | 6–24 MB | 400–533 MHz | 1 | 2 | 75–104 W | Features virtualization and multithreading; lacks hardware IA-32 support |
| Itanium 9100 series | ||||||||||
| Montvale | 90 nm | 2007-10-31 | 1.42–1.66 GHz | 256 KB (D)+1 MB (I) | 8–24 MB | 400–667 MHz | 1 | 1–2 | 75–104 W | Introduces core-level lockstep and demand-based switching |
| Itanium 9300 series | ||||||||||
| Tukwila | 65 nm | 2010-02-08 | 1.33–1.73 GHz | 256 KB (D)+512 KB (I) | 10–24 MB | QPI at 4.8 GT/s | 1 | 2–4 | 130–185 W | Debuted Intel QuickPath Interconnect replacing FSB; supports Turbo Boost |
| Itanium 9500 series | ||||||||||
| Poulson | 32 nm | 2012-11-08 | 1.73–2.53 GHz | 256 KB (D)+512 KB (I) | 20–32 MB | QPI at 6.4 GT/s | 1 | 4–8 | 130–170 W | Doubles issue width to twelve instructions per cycle; includes Instruction Replay technology and dual-domain hyperthreading |
| Itanium 9700 series | ||||||||||
| Kittson | 32 nm | 2017-05-11 | 1.73–2.66 GHz | 256 KB (D)+512 KB (I) | 20–32 MB | QPI at 6.4 GT/s | 1 | 4–8 | 130–170 W | No architectural enhancements over Poulson; slight clock speed increase on highest model |
High-end server market
Upon its debut in 2001, Itanium's performance trailed behind the well-established RISC and CISC processors. The emulation of existing x86 applications was notably inefficient, with benchmark results comparable to a 100 MHz Pentium, despite the availability of 1.1 GHz Pentium processors. Itanium struggled to capture meaningful market share against IA-32 and RISC competitors, experiencing further decline as x86-64 systems emerged, offering superior compatibility.
In 2009, journalist John C. Dvorak described Itanium as "one of the great fiascos of the last 50 years." Tech commentator Ashlee Vance highlighted that delays and underwhelming performance had "turned the product into a joke in the chip industry." Meanwhile, Donald Knuth pointed out that the anticipated compiler technology for Itanium was "basically impossible to write."
Both Red Hat and Microsoft announced intentions to discontinue Itanium support due to limited demand; nonetheless, distributions such as Gentoo and Debian continued to offer support. On March 22, 2011, Oracle Corporation halted development of new HP-UX products for Itanium but maintained support for existing software. This led HP to sue Oracle for breach of contract, citing an agreement obligating Oracle to support Itanium software until HP ceased its server production. A 2012 court decision sided with HP, compelling Oracle to resume support. In June 2016, Hewlett Packard Enterprise, which succeeded HP's server division, was awarded $3 billion in damages; Oracle’s appeal was rejected in 2021.
According to a former Intel executive, Itanium became profitable for Intel by late 2009. At that time, HP controlled over 95% of the Itanium server market, with HP-UX serving as the dominant operating system. On March 22, 2011, Intel reaffirmed its dedication to the platform, confirming multiple upcoming chip generations were progressing on schedule.
Other markets
While Itanium found niche success within high-end computing sectors, Intel originally intended it to supplant the original x86 architecture entirely. However, AMD took a different direction by developing the less radical x86-64, a 64-bit extension compatible with x86 that gained Microsoft’s endorsement. This forced Intel to incorporate similar extensions into its processors. These architectures enable native execution of 32-bit applications while supporting 64-bit memory addressing and enhancements for modern software. Currently, this design dominates desktop and laptop markets. Some manufacturers like SGI released Itanium-based workstations, though such products are no longer available.