Racetrack memory
| Industry | Computer memory research |
|---|---|
| Founder | Stuart Parkin |
| Headquarters | San Jose, California , United States |
Key people | Stuart Parkin (physicist) |
| Products | Racetrack memory (experimental) |
Racetrack memory, also known as domain-wall memory (DWM), represents an innovative form of non-volatile memory currently under experimental development. This technology originated at IBM's Almaden Research Center led by physicist Stuart Parkin and is additionally explored at the Max Planck Institute of Microstructure Physics. In 2008, researchers unveiled a prototype capable of storing 3 bits. Upon successful commercialization, racetrack memory promises storage densities that could exceed those of existing solid-state technologies such as flash memory.
Description
The operation of racetrack memory relies on a spin-polarized electric current to shift magnetic domains along nanometer-scale permalloy wires, typically measuring about 200 nm in width and 100 nm in thickness. These magnetic domains move past read/write heads which encode and retrieve data bits. The memory architecture comprises numerous such wires paired with corresponding read/write components. While conceptually reminiscent of earlier concepts like bubble memory and delay-line memory, racetrack memory distinguishes itself by utilizing advanced spintronic magnetoresistive sensors, enabling significantly higher bit densities through much smaller magnetic domain sizes.
Future manufacturing projections aimed for wire widths near 50 nm. Two principal structural designs were investigated: planar wire arrays with adjacent read/write heads, and vertically oriented U-shaped wires arranged over a substrate grid. The vertical configuration permits longer wire lengths without enlarging the device footprint but may result in slower random access times due to extended domain travel distances. Both layouts deliver comparable data throughput rates. A key production hurdle lies in the scalability of fabricating the complex three-dimensional vertical structures on a mass scale.
Comparison to other memory devices
Estimates from 2008 suggested that racetrack memory could access random bits within 20–32 ns, contrasting sharply with hard drives’ approximate 10,000,000 ns latency and conventional DRAM’s 20–30 ns range. Incorporating a "reservoir" mechanism might further reduce access times to roughly 9.5 ns. Overall throughput for racetrack memory was projected between 250 and 670 Mbit/s, compared to DDR3 DRAM’s 12,800 Mbit/s, high-performance hard drives at about 1,000 Mbit/s, and flash storage ranging from 1,000 to 4,000 Mbit/s. Although SRAM offers much lower latency (~0.2 ns), it comes at a higher cost. The physical cell size for racetrack memory was approximately 140 F² with feature dimensions around 45 nm as of 2011.
Racetrack memory is among several emerging candidates aiming to replace DRAM and Flash by providing a universal memory solution. Competing technologies include magnetoresistive RAM (MRAM), phase-change memory (PCRAM), and ferroelectric RAM (FeRAM). These alternatives generally achieve densities comparable to or below that of flash while avoiding flash's limitations related to write endurance. Field-MRAM delivers rapid access times (~3 ns) but suffers from relatively large cell sizes (25–40 F²), making it more appropriate as an SRAM substitute rather than for mass storage applications. PCRAM attains high density (~5.8 F²) and moderate speeds (~50 ns), yet still trails racetrack memory in overall performance and density metrics. For instance, racetrack memory’s capability to manipulate multiple bits per track results in an effective cell size close to 4 F², exceeding PCRAM’s efficiency. Other emerging memories like resistive RAM (RRAM) or spin-torque transfer MRAM provide faster switching (~10 ns) but do not match racetrack’s bit density.
Memory technologies are frequently evaluated based on cell size expressed in units of F² (the square of the feature size). Although both flash and racetrack memories store several bits per cell, these comparisons remain meaningful. Hard disk drives approach theoretical limits near 650 nm² per bit (~1 Tbit/in²). DRAM cells occupy roughly 6 F², whereas SRAM cells are considerably larger at about 120 F². Among non-volatile memories commonly used, NAND flash exhibits the highest density at approximately 4.5 F² per cell effectively storing three bits (equivalent to about 1.5 F² per bit); NOR flash is slightly less dense with an effective size near 4.75 F² per bit. Racetrack memory’s vertical U-shaped design can hold approximately 10 to 20 bits per cell within a physical footprint around 20 F². Access times along the track vary between ~10 ns and ~1000 ns due to domain wall propagation occurring at a constant velocity near 100 m/s.
Development challenges
Initial prototype devices encountered a significant obstacle: magnetic domains could only be shifted slowly along wires, necessitating microsecond-scale current pulses. This limitation resulted in speeds similar to those of hard drives, roughly 1000 times slower than anticipated. Investigations revealed that tiny defects within the crystal lattice caused domain walls to become immobilized. Through X-ray microscope imaging, it was demonstrated that in the absence of such defects, domain walls could be propelled by pulses lasting just a few nanoseconds, achieving velocities near 110 m/s.
The voltage required to move domains increases proportionally with wire length, and very high current density levels—exceeding 108 A/cm2—are necessary; for instance, a wire with a 30 nm by 100 nm cross-section demands currents above 3 mA. This results in power consumption surpassing that of competing technologies such as spin-transfer torque memory (STT-RAM) or flash memory.
Another difficulty involves the unpredictable, stochastic behavior of domain wall motion, which can halt or shift erratically. Strategies to address this include fabricating notches along nanowire edges and employing staggered nanowire designs to accurately anchor domain walls. Experimental validation has confirmed the success of staggered domain wall memory configurations. More recent innovations focus on non-structural methods like locally altering magnetic characteristics through compositional adjustments. Techniques including annealing-induced diffusion and ion implantation have been applied effectively to regulate domain wall pinning.
See also
- Giant magnetoresistance (GMR) effect
- Magnetoresistive random-access memory (MRAM)
- Spintronics
- Spin transistor