SGI Origin 2000
| Company type | Public |
|---|---|
| Industry | Computer hardware |
| Founded | November Expression error: Unrecognized word "sgi"., 1981 |
| Headquarters | Mountain View , United States |
| Products | Origin 2000 series servers |
The SGI Origin 2000 series represents a range of mid- to high-tier server systems developed by Silicon Graphics (SGI), launched in 1996 as the successors to the SGI Challenge and POWER Challenge models. These machines operated on the IRIX platform, starting with version 6.4 and later upgrading to 6.5. A variant equipped with advanced graphics capabilities was known as the Onyx2, while the entry-level system sharing similar architecture but differing in hardware design was the Origin 200. The Origin 2000 line was eventually replaced by the Origin 3000 in July 2000 and officially discontinued on June 30, 2002.
Models
Unveiled on October 7, 1996, under the project codenames Lego or SN0, this initiative marked a transition from the earlier symmetric multiprocessor architecture of the SGI Challenge series to a scalable node-based design.
| Model | CPU Count | Maximum Memory | I/O Slots | Chassis Type | Launch Date | End of Life |
|---|---|---|---|---|---|---|
| Origin 2100 | 2 to 8 | Up to 16 GB | 12 XIO | Deskside | Unknown | May 31, 2002 |
| Origin 2200 | 2 to 8 | Up to 16 GB | 12 XIO | Deskside | Unknown | May 31, 2002 |
| Origin 2400 | 8 to 32 | Up to 64 GB | 96 XIO | 1 to 4 racks | Unknown | May 31, 2002 |
| Origin 2800 | 32 to 128 (256 and 512 unsupported) | Up to 256 GB (512 GB unsupported) | 384 XIO | 1 to 9 racks (with Meta Router) | Unknown | May 31, 2002 |
The Origin 2100 resembles other models but cannot be upgraded without replacing major components.
While SGI promoted configurations supporting up to 128 processors for the Origin 2000, systems exceeding this CPU count were marketed under the "CRAY Origin 2000" brand following SGI's acquisition of Cray Research. Although versions capable of accommodating up to 512 CPUs and corresponding memory existed, they were not widely commercialized—one unit was utilized at SGI's Eagan facility for evaluation purposes, and two were sold to NASA Ames Research Center for specialized scientific computations. These top-tier configurations carried a price tag near $40 million each and were soon overtaken by the more scalable and economically viable Origin 3000 series.
Certain clients obtained non-publicized configurations featuring up to 256 CPUs.
The most extensive deployment was the ASCI Blue Mountain supercomputer at Los Alamos National Laboratory, which integrated forty-eight Origin 2000 units each with 128 processors, interconnected through HIPPI, culminating in a total of 6,144 CPUs. During performance assessments, this system ranked second on the TOP500 list, delivering sustained throughput reaching approximately 2.1 teraflops and peak performance exceeding 2.5 teraflops. Additionally, Los Alamos operated a smaller twelve-node cluster totaling 1,536 CPUs.
The National Center for Atmospheric Research maintained a notable Origin 2000 system named "Ute," equipped with 128 processors from May 1998 until July 2002, alongside a smaller sixteen-CPU dataproc machine. NASA Ames' collection included systems designated Harvard Lomax (512 CPUs), Joseph Steger (128 CPUs), Grace Hopper (64 CPUs), and Alan Turing (24 CPUs).
Hardware
The architecture of each Origin 2000 module incorporates nodes connected via a backplane, accommodating up to four node boards, two router boards, and twelve slots for XIO expansion cards. These modules are installed within either a deskside enclosure housing one module or racks capable of holding up to two modules each. Systems requiring more than two modules employ multiple rack units.
| Enclosure Type | Width | Height | Depth | Weight |
|---|---|---|---|---|
| Deskside | 53 cm (21 inches) |
65 cm (25.5 inches) |
58 cm (23 inches) |
98 kg (215 lb) |
| Rack | 71 cm (28 inches) |
185 cm (73 inches) |
102 cm (40 inches) |
317 kg (700 lb) |
Dimensions represent maximum configuration values.
While sharing some architectural elements with the Origin 2000, the Origin 200 model features a distinct physical design that does not support scalability.
Architecture
The Origin 2000 system is composed of multiple nodes interconnected through a distributed shared memory framework, commonly referred to as Scalable Shared-Memory Multiprocessing (S2MP). It utilizes NUMAlink (initially known as CrayLink) for its system-wide interconnections. Nodes interface with router boards, which in turn are connected by NUMAlink cables, establishing a dense fat hypercube network topology. For configurations with more than 64 processors, a hierarchical fat hypercube arrangement is implemented. To improve bandwidth and lower latency, additional NUMAlink Xpress connections can be added between unused router ports; however, this enhancement is feasible only in 16- or 32-processor setups due to architectural limitations.
This design traces its origins to the DASH project at Stanford University, overseen by John L. Hennessy, with significant contributions from the principal designers of the Origin system.
Router boards
The Origin 2000 incorporates four types of router boards, each designed to support an increasing number of nodes.
Null Router
This router links two nodes within the same module but lacks external connectors, making systems using it non-expandable.
Star Router
Capable of connecting up to four nodes, the Star Router requires pairing with a Standard Router for proper functionality.
Standard Router (Rack Router)
Supporting up to 32 nodes, this router includes an ASIC named SPIDER (scalable pipelined interconnect for distributed endpoint routing), which handles NUMAlink routing tasks. The SPIDER chip features six ports with unidirectional links interconnected via a crossbar switch to facilitate communication among all ports.
Meta Router (Cray Router)
Designed to work in conjunction with Standard Routers, the Meta Router extends connectivity beyond 32 nodes, supporting up to 64 nodes.
Nodes
Each node in the Origin 2000 is a single printed circuit board measuring 16" by 11", housing one or two processors, main memory, directory memory, and the Hub ASIC. Nodes connect to the backplane through a 300-pad CPOP connector that integrates both the NUMAlink router network and the XIO I/O subsystem.
Processor
Processors and their associated secondary caches reside on HIMM daughter cards inserted into the node board. The original IP27 board offered one or two 180 MHz R10000 processors with 1 MB secondary caches; higher-end variants featured dual 195 MHz R10000s equipped with 4 MB caches. In 1998, the IP31 board was introduced with dual 250 MHz R10000 processors and 4 MB caches, later upgraded to support dual 300, 350, or 400 MHz R12000 processors. The models running at 300 and 400 MHz had 8 MB L2 caches, while the 350 MHz variant included a 4 MB cache. Toward the end of its lifecycle, an IP31 model supported dual 500 MHz R14000 processors with 8 MB L2 caches.
Main memory and directory memory
Each node can accommodate up to 4 GB of memory through sixteen proprietary ECC SDRAM DIMM slots ranging from 16 to 256 MB each. The memory bus width is 144 bits (128 bits for data plus 16 bits for ECC), requiring modules to be installed in pairs. To ensure cache coherence across as many as 32 processors within the distributed shared memory environment, memory modules incorporate directory memory that monitors remote cache states. Systems exceeding 32 processors necessitate additional directory memory installed in eight dedicated DIMM slots.
Hub ASIC
The Hub ASIC serves as the connection point linking processors, memory, and XIO to the NUMAlink 2 interconnect system. It is composed of five primary components: the crossbar ("XB"), I/O interface ("II"), network interface ("NI"), processor interface ("PI"), and memory/directory interface ("DM"), which also acts as the memory controller. These components communicate through FIFO buffers that are connected to the crossbar. When two processors are attached to the Hub ASIC, they function independently rather than in a SMP configuration, with their buses multiplexed over a single processor interface to minimize pin usage. Operating at 100 MHz, the Hub ASIC incorporates 900,000 gates manufactured using a five-layer metal fabrication process.
I/O subsystem
At the heart of the I/O subsystem lies the Crossbow (Xbow) ASIC, which resembles the SPIDER ASIC but is streamlined for compatibility with the XIO protocol. This design supports eight ports—two dedicated to node boards and six allocated for XIO cards—surpassing SPIDER’s six-port capacity. Although the native bus is XIO, compatibility with PCI-X and VME64 is achieved through XIO bridges.
Every system comes equipped with an IO6 base I/O board, an XIO card that offers:
- One 10/100BASE-TX network port
- Two Serial ports via dual UART interfaces
- One internal Fast 20 UltraSCSI single-ended port
- One external wide UltraSCSI single-ended port
- One real-time interrupt output for frame synchronization
- One edge-triggered real-time interrupt input
- Storage components including Flash PROM, NVRAM, and a real-time clock
The IO6G ("Graphics") board enhances functionality by adding two serial ports along with keyboard and mouse connectors, which are essential for systems utilizing Onyx Graphics cards to support input peripherals.