SGI Challenge
| Company type | Product line |
|---|---|
| Industry | Computer hardware |
| Predecessor | Power Series |
| Founded | 1990s |
| Headquarters | United States |
| Products | Server and supercomputer systems |
| Parent | Silicon Graphics |
The Challenge series, internally referred to as Eveready for deskside models and Terminator for rackmount configurations, represents a range of server and supercomputer systems created by Silicon Graphics during the early to mid-1990s. These systems succeeded the earlier Power Series lineup (which is unrelated to IBM Power Systems). In 1996, the Challenge lineup was superseded by the NUMAlink-based Origin 200 and Origin 2000 platforms.
Models
The Challenge product line consists of three primary variants. The initial "Challenge" model utilized the 64-bit R4400 processor. With the arrival of the R8000, these systems were enhanced to accommodate additional processors and memory capacity, marketed under the "POWER Challenge" name. Subsequently, the architecture was updated to incorporate R10000 microprocessors: earlier R10000-equipped units were designated "Challenge 10000," while POWER Challenge models featuring R10000 CPUs were labeled "POWER Challenge 10000."
Models bearing the "GR" suffix ("Graphics Ready") were compatible with the RealityEngine and InfiniteReality graphics subsystems. Conventional models operated as servers or supercomputers without integrated graphics capabilities.
Challenge
| Model | CPU Count | Processor | Processor Speed (MHz) | L2 Cache | Memory Capacity | Form Factor | Release Year |
|---|---|---|---|---|---|---|---|
| DM (Departmental) |
1, 2 or 4 | R4400 | 100, 150, 200 or 250 |
1 MB | ? | Deskside | 1994 |
| L (Large) |
1 to 12 | R4400 | 100, 150, 200 250 |
1 or 4 MB | Up to 2 GB | Deskside | 1993 |
| GR (Graphics Ready) |
2, 4, 8, 12, 16 or 24 | R4400 | 100, 150, 200 250 |
1 or 4 MB | ? | Rackmount | ? |
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 | R4400 | 100, 150, 200 or 250 | 1 or 4 MB | 16 GB | Rackmount | 1993 |
Challenge 10000
| Model | CPU Count | Processor | Processor Speed (MHz) | L2 Cache Size | Memory Capacity | Chassis Type | Launch Date |
|---|---|---|---|---|---|---|---|
| L (Large) |
1 to 12 | R10000 | 195 | 1 or 2 MB | Up to 2 GB | Deskside | ? |
| GR (Graphics Ready) |
2, 4, 8, 12, 16 or 24 | R10000 | 195 | 1 or 2 MB | ? | Rackmount | ? |
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 | R10000 | 195 | 1 or 2 MB | 16 GB | Rackmount |
POWER Challenge
Introduced on January 28, 1993, the POWER Challenge was designed to compete with supercomputers such as those from Cray Research. Silicon Graphics asserted that a single POWER Challenge microprocessor could rival the performance of a Cray Cray Y-MP. The system became available in mid-1994 and incorporated the MIPS R8000 processor family—consisting of the R8000 CPU and R8010 floating-point unit—augmented by a "streaming" cache mechanism. The R8000 was engineered for intensive floating-point scientific calculations and included features like fused multiply–add operations alongside a substantial cache.
In a subsequent update in 1995, SGI enhanced the POWER Challenge by equipping it with faster R8000 CPUs running at 90 MHz. This upgrade raised its computational throughput to approximately 6.48 GFLOPS—a gain of about one GFLOPS compared to the earlier version operating at 75 MHz.
| Model | CPU Quantity | Processor | Processor Speed (MHz) | L2 Cache | Memory Capacity | Chassis | Release Date | End of Production |
|---|---|---|---|---|---|---|---|---|
| L (Large) |
1 to 6 | R8000 | 75 or 90 | 4 MB | max. Up to 6 GB | Deskside
?|21 January 1997 | ||
| 'GR (Graphics Ready) |
'1 to '12 | 'R8000' | '75 or '90' | '4 MB' | '?' | 'Rackmount' | '?' | '21 January '1997' |
| 'XL (Extra Large) |
'2 to '18' | 'R8000' | '75 or '90' | '4 MB' | '64 MB to '16' GB' | 'Rackmount' | '?' | '21 January '1997' |
POWER Challenge 10000
Launched in January 1996, the POWER Challenge 10000 introduced the R10000 processor to the lineup, replacing earlier models based on the R4400 and R8000 processors found in the Challenge and POWER Challenge series. These older systems remained available alongside the new model for a transitional period. The updated "IP25" CPU board accommodated between one and four processors along with their secondary cache memories, much like its predecessor, the IP19 board.
| Model | Number of CPUs | Processor | Processor Speed (MHz) | Secondary Cache | Memory Capacity | Chassis Type |
|---|---|---|---|---|---|---|
| L (Large) |
1 to 12 | R10000 | 195 | 1 or 2 MB | Up to 6 GB | Deskside |
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 |
R10000 | 195 | 1 or 2 MB | 64 MB to 16 GB | Rackmount |
CHALLENGEarray
The CHALLENGEarray and POWER CHALLENGEarray represent clusters composed of multiple Challenge or POWER Challenge servers. The CHALLENGEarray can scale from 2 up to 288 R10000 CPUs, whereas the POWER CHALLENGEarray supports between 2 and 144 R8000 processors with a maximum memory capacity of 128 GB. The POWER CHALLENGEarray was introduced on November 15, 1994.
Additional Models
Silicon Graphics also offered the Challenge M and Challenge S, which were essentially rebranded Indigo2 and Indy workstations stripped of their graphics hardware. While these shared the Challenge branding and signature blue casing, they functioned as entry-level servers within the Challenge product line but did not share multiprocessing architectural features with other Challenge systems.
Physical Description
Deskside models are predominantly black with a vertical blue accent on the right side, whereas rackmount versions display a blue front panel accented by a central black strip containing the system controller interface. Dimensions for deskside units are approximately 54 cm (21 in) wide, 65 cm (26 in) tall, and 74 cm (29 in) deep, weighing no less than 89 kg (195 lbs). Rackmount configurations measure about 69 cm (27 in) wide, stand 159 cm (62.3 in) high, extend 122 cm (48 in) deep, and can weigh up to 544 kg (1200 lbs), powered by a robust 1,900-watt power supply.
System Architecture
The Challenge series operates as a shared-memory multiprocessor platform built from modular nodes that connect via a midplane equipped with Ebus slots alongside the POWERpath-2 system bus. This bus provides a data width of 256 bits and an address width of 40 bits running at a frequency of 47.6 MHz, resulting in a continuous bandwidth of approximately 1.2 GB/s.
Midplanes for DM and L models feature five Ebus slots capable of hosting three CPU boards, one memory board, or two POWERchannel-2 interface boards, supplemented by five VME expansion slots. The XL midplane increases capacity substantially with fifteen Ebus slots that can accommodate nine CPU boards, eight memory boards, or five POWERchannel-2 interface boards. Additionally, it includes six VME expansion slots and three slots dedicated to power boards.
Circuit Boards
The Challenge systems employ the POWERpath-2 family of circuit boards, internally known as "Everest," which includes CPU boards IP19, IP21, and IP25, along with the MC3 memory board and IO4 POWERchannel-2 interface board.
CPU boards
The microprocessors are housed on CPU boards, which come in three variants: IP19, IP21, and IP25. The IP19 board accommodates either two or four R4400 microprocessors and incorporates five CPU Interface ASICs to manage data and address pathways. The IP21 supports one or two R8000 microprocessors, while the IP25 can support one, two, or four R10000 microprocessors.
MC3
Memory capacity is provided by the MC3 board, which contains thirty-two SIMM slots and two leaf controllers. It is compatible with 16 MB "high-density" and 64 MB "super-density" FPM ECC SIMMs, allowing for a total memory range of 64 MB up to 2 GB. SIMMs must be installed in sets of four.
The memory architecture consists of eight banks divided into two leaves, enabling interleaving across multiple leaves. The memory bus is 576 bits wide, composed of a 512-bit data channel alongside a 64-bit ECC channel. Each leaf controller oversees four banks and half of a memory transaction, interfacing with 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.
Memory operations transfer 128 bytes per transaction, aligning with the cache line size used by MIPS microprocessors. Read operations complete within two memory clock cycles and are buffered before being sent over four clock cycles on the POWERpath-2 bus.
ECC mechanisms safeguard the SIMMs by correcting single-bit errors and identifying double-bit errors. The board includes built-in self-test functionality that runs during power-up or reset; if any faults are found, the firmware disables the affected memory banks accordingly.