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UNIVAC 1100/2200 series

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UNIVAC 1100/2200 series
Company typeComputer hardware series
IndustryComputer systems
PredecessorVacuum tube UNIVAC 1101 to 1105 series
Founded1962
FounderSperry Rand
FateSupported by Unisys under ClearPath Dorado Series branding
Area served
Worldwide
ProductsUNIVAC 1107, 1108, 1106 and related models
OwnerSperry Rand (original), Unisys (current)

The UNIVAC 1100/2200 series represents a family of compatible 36-bit computer systems, initiated with the UNIVAC 1107 in 1962, originally manufactured by Sperry Rand. Currently, it is supported by Unisys under the ClearPath Dorado Series branding. Despite the solid-state 1107 succeeding earlier vacuum-tube models in numbering, these initial machines were not compatible with their solid-state descendants.

Data formats

  • Fixed-point data, encompassing both integer and fractional types:
    • Full word – 36-bit (ones' complement)
    • Half word – two 18-bit segments per word (unsigned or ones' complement)
    • Third word – three 12-bit segments per word (ones' complement)
    • Quarter word – four 9-bit segments per word (unsigned)
    • Sixth word – six 6-bit segments per word (unsigned)
  • Floating point:
    • Single precision – 36 bits total: one sign bit, an 8-bit characteristic, and a 27-bit mantissa
    • Double precision – 72 bits total: one sign bit, an 11-bit characteristic, and a 60-bit mantissa
  • Alphanumeric:
    • FIELDATA – a UNIVAC variant of a 6-bit code allowing six characters within each 36-bit word (no lowercase support)
    • ASCII – uses 9 bits per character (8 bits utilized), fitting four characters into a single 36-bit word

Instruction format

Each instruction is composed of 36 bits divided into the following fields:

f (6 bits) - function code (opcode),
j (4 bits) - designates partial word, J-register, or minor function,
a (4 bits) - specifies register (A, X, or R) or I/O function,
x (4 bits) - index register (X) identifier,
h (1 bit) - index register increment flag,
i (1 bit) - indirect addressing flag,
u (16 bits) - address or operand field.

Registers

Address Register Contents
000 Unused Unused
001 X1 Increment Modifier
... ... Increment Modifier
013 X11 Increment Modifier
014 X12/A0 Overlap (X or A)
... ... Overlap (X or A)
017 X15/A3 Overlap (X or A)
020 A4 Accumulator
... ... Accumulator
033 A15 Accumulator
034 A15+1 Unassigned (A)
... ... Unassigned (A)
037 A15+4 Unassigned (A)
... Executive Protected Executive
101 R1 Special (R)
... ... Special (R)
117 R15 Special (R)
... Executive Protected Executive
177 Executive Protected Executive

Models such as the UNIVAC 1108 and UNIVAC 1106 feature a high-speed "general register stack" comprising 128 registers, which correspond to the current data space in main memory beginning at address zero. This set includes user and executive versions of the A, X, R, and J registers along with specialized executive registers.

User-accessible registers consist of fifteen index registers labeled X1 through X15, sixteen accumulators named A0 to A15, and fifteen special function user registers designated R1 to R15. Among these, four J registers and three staging registers utilize certain special R registers.

Importantly, the final four index registers (X12 through X15) share storage locations with the first four accumulators (A0 to A3), allowing dual-use interpretations of data. Due to this overlap, there are four accumulators without assigned functions (A15+1 through A15+4), which can only be accessed via memory operations; additionally, double-word instructions targeting A15 also affect A15+1.

Vacuum tube computers lacked interoperability

Prior to the introduction of the UNIVAC 1107, UNIVAC developed a series of vacuum tube-based machines, numbered from 1101 through 1105. These computers featured distinct architectures and varying word lengths, resulting in incompatibility both among themselves and with the subsequent 1107 line. All these models utilized vacuum tube technology and frequently relied on drum memory as their primary storage medium. Several of these systems were designed by Engineering Research Associates (ERA), which was later absorbed by UNIVAC.

The UNIVAC 1101 (also known as ERA 1101) was engineered by ERA and manufactured by Remington Rand during the 1950s but never entered commercial sales. It originated from Navy Project 13, corresponding to the binary number 1101. The UNIVAC 1102 was developed specifically for the U.S. Air Force by ERA. The 36-bit UNIVAC 1103, released in 1953, along with its enhanced successor, the UNIVAC 1103A in 1956, were pioneering commercial machines that adopted core memory rather than relying on the earlier Williams tube. The UNIVAC 1105, introduced in 1958, served as the successor to the 1103A.

The UNIVAC 1104 was a specialized 30-bit adaptation of the 1103 crafted for Westinghouse Electric in 1957 to support the BOMARC Missile Program. By the time the BOMARC missiles were deployed in the 1960s, this system had been supplanted by a more advanced computer—a variant of the AN/USQ-20, identified as G-40.

UNIVAC 1100 series with compatible architecture

These models shared a unified design framework and word size, employing transistor-based circuitry initially and later incorporating integrated circuit technology. Early iterations utilized core memory (with the exception of the 1110, which implemented plated-wire memory) before transitioning to semiconductor memory around 1975.

1107

Debuting in October 1962, the UNIVAC 1107 represented Sperry Univac’s first solid-state machine within its UNIVAC 1100 lineup. Dubbed the Thin-Film Computer due to its use of thin-film memory for storing registers, it introduced a single-address instruction format and supported up to 65,536 words of 36-bit core memory. Its registers were housed in a faster thin-film memory consisting of 128 words, enabling index addressing without incurring additional cycle delays. Only thirty-six units were ever sold.

Core memory was expandable in blocks of 16,384 words up to a maximum capacity of 65,536 words distributed over two banks, featuring a cycle time of four microseconds (effectively reduced to two microseconds when overlapping instruction and data fetches). The thin-film register stack boasted an access time of approximately 300 nanoseconds and facilitated rapid index modifications through sixteen index registers.

The architecture accommodated sixteen input/output (I/O) channels that employed thin-film memory for direct-to-memory I/O registers. Executing programs from unused thin-film locations was not permitted.

Both UNISERVO IIA and UNISERVO III tape drives were supported; these drives were compatible with metallic or mylar tape. Additionally, an FH880 drum memory unit offered expanded spooling and file storage capacity of roughly 300,000 words (36 bits each) operating at a speed of 1800 RPM.

Excluding peripherals, the weight of the complete 1107 system was approximately .

Univac provided a batch processing operating system called EXEC I. Computer Sciences Corporation developed an optimizing compiler for Fortran IV, an advanced macro-capable assembler named SLEUTH, as well as a versatile linking loader.

Illustrative costs

Below is a sample budget outline for a UNIVAC 1107 dated 1963.

Component Quantity Unit cost Total expense
Univac 1107 central processor 1 $888,750 $888,750
Dual-bank core memory with 65,536 words 1 $798,750 $798,750
Card Reader - 600 cards per minute 1 $17,500 $17,500
Card reader control and synchronization unit 1 $83,250 $83,250
High-speed online printer - 600 lines per minute 1 $25,000 $25,000
High-speed printer control and synchronization unit 1 $77,500 $77,500
Uniservo II-A drives 4 $20,000 $80,000
Uniservo II-A control and synchronization units 2 $77,500 $155,000
Uniservo II-A power supply unit 1 $25,300 $25,300
Uniservo III-A drives 14 $36,500 $511,000
Uniservo III-A dual-channel control and synchronization units 2 $240,000 $480,000
Uniservo III-A power supplies 2 $25,300 $50,600
Medium-speed papertape subsystem 1 $32,250 $32,500
FH 880 drum storage - 4,718,592 characters (786,432 words) 2 $92,000 $184,000
FH 880 drum control and synchronization unit 1 $72,000 $72,000
Extra teletypewriters connected to console channel 2 $10,000 $19,100
Total cost $3,500,000
Magnetic tapes 10,000 $30 each $300,000
Spare components $145,000

1108

Debuting in 1964, the UNIVAC 1108 succeeded the UNIVAC 1107 by replacing thin-film registers with integrated circuits and employing smaller yet faster core memory. Among its notable enhancements were two 18-bit base registers that facilitated dynamic relocation of instructions and data to support multiprogramming. Memory protection was strengthened through base and limit registers assigned separately to instruction (I-bank) and data (D-bank) segments, enabling distinct physical memory banks for optimized performance. The Processor State Register (PSR) introduced control bits that managed storage protection and user privilege levels.

The system incorporated additional hardware instructions tailored for double precision calculations and double-word processing. Its CPU architecture supported up to sixteen input/output channels. Most of the CPU was constructed using discrete logic cards connected via wire-wrapped backplanes; only the Integrated Control Register (ICR) stack utilized integrated circuits. Core memory capacity reached up to 64K words with a fundamental cycle time of 750 nanoseconds.

In 1965 Sperry Rand released the UNIVAC 1108 II (also called 1108A), which introduced multiprocessing capabilities by supporting up to three CPUs alongside two independent programmable I/O controllers (IOCs). This configuration allowed concurrent execution of five separate processes: three CPU-driven programs plus two input/output operations. A new "test-and-set" instruction was implemented to enable CPU synchronization.

Although initial sales forecasts estimated approximately 43 units sold, production ultimately totaled 296 machines. The multiprocessor setup accommodated as many as four memory banks totaling 262,144 words with eight ports each dedicated to CPUs and IOCs. Typical configurations featured one or two CPUs with eight or optionally sixteen I/O channels and two or three core memory cabinets; systems with three CPUs and four cabinets were uncommon due to high costs.

The IOC cabinet expanded I/O channel availability for substantial mass storage requirements; only a limited number were manufactured with United Air Lines as the principal customer.

The UNIVAC Array Processor (UAP) represented an even rarer standalone mathematical coprocessor designed for the 1108A. It housed four arithmetic units within a separate cabinet capable of accessing memory from two independent systems. The UAP accelerated array-processing operations such as fast Fourier transforms (FFT), functioning independently from the CPUs and signaling task completion through interrupts. Notable users included Shell Oil Company as well as Canadian firms Digitech and Gulf Canada.

When Sperry Rand transitioned from core memory to semiconductor-based memory technology, the system was renamed UNIVAC 1100/20, with the final digit indicating the number of CPUs present (for example, 1100/22 denoted a dual-CPU system).

1106

The initial 1107 and early 1108 models were primarily designed for the engineering and scientific computing sectors, as evidenced by the 1100 Series User Group known as the UNIVAC Scientific Exchange (USE). These batch-processing operating systems mainly accommodated FORTRAN and, to a lesser degree, ALGOL. However, as commercial computing needs expanded—particularly for COBOL applications—these platforms proved insufficient. In response, UNIVAC developed the 1108A multiprocessor system alongside the EXEC 8 operating system. Although scientific workloads were typically CPU-intensive, business-oriented tasks tended to be I/O-bound, causing CPUs on 1108A multiprocessors to remain idle up to half of the time. This realization prompted the creation of a more affordable, lower-performance system tailored to the growing commercial sector.

Released in December 1969, the UNIVAC 1106 shared nearly identical hardware and instruction sets with the 1108 but was engineered with cost reduction in mind. It supported up to two CPUs but did not include IOC support. The primary distinction from the 1108A was in its timing circuitry; early 1106 units operated at half the speed of the 1108. Cost savings were further achieved by offering configurations with as few as four word channels, which limited peripheral I/O capabilities. Subsequent models incorporated slower, less expensive memory systems compared to those in the 1108. In total, Sperry Univac sold 338 processors within 1106 configurations.

When Sperry Rand transitioned from core memory to semiconductor memory, this hardware was rebranded as the UNIVAC 1100/10.

  • Note: The EXEC 8 "idle loop" refers to periods when CPUs awaited I/O completion, executing minimal internal memory cycles to maximize core memory availability for active processors.*

1110

Launched in 1972, the UNIVAC 1110 advanced multiprocessing capabilities by enabling sixteen-way memory access and supporting up to six CAUs (Command Arithmetic Units) along with four IOAUs (Input Output Access Units). The CAU expanded memory addressing from 18 bits (as seen in the 1108/1106) to 24 bits, allowing for up to 16 million words of addressable memory. Plated-wire memory replaced core memory; each cabinet contained eight separate 8K modules (totaling 64K), with scalability up to four cabinets. Additional Extended Memory cabinets could be linked via daisy-chaining for further storage—up to one million words—using an Extended Storage Controller responsible for address translation.

The minimum setup required two CAUs and one IOAU; the largest configuration (6x4) was exclusively deployed by NASA. The CAU marked UNIVAC’s first pipelined processor design, capable of processing four instructions concurrently. The IOAU functioned independently with its own access path to both main and extended memory, ensuring that I/O operations did not compete with CPU memory cycles. It supported up to twenty-four compatible 36-bit Word Channels and housed the Hardware Maintenance Panel—commonly visible in system images since CAU cabinets lacked status indicators. Additionally, the CAU introduced 'Byte Instructions' that extended the processor’s instruction set.

Key components utilized high-density connectors and wire-wrapped backplanes similar to previous models but replaced discrete logic elements with advanced transistor–transistor logic (TTL) integrated circuits. The CAU alone contained over one thousand circuit cards.

With semiconductor memory supplanting plated-wire technology, Sperry Rand marketed this system as the UNIVAC 1100/40. The final digit in this naming scheme indicated CPU count; for instance, "40" represented four CPUs. The updated main memory cabinet doubled module capacity to sixteen-kilobyte static RAM modules (131K words per cabinet), increasing maximum main memory size to 524K words. The CAU featured four base and limit registers that enabled dynamic switching among four separate 64K banks during program execution.

Sperry Rand sold roughly 290 processors within the 1110 series.

  • Note: TTL integrated circuits employed in the 1110 (and later in the 1100/40) were cutting-edge ceramic 14-pin DIPs operating at a +5-volt power supply.*

Semiconductor memory series

In 1975, Sperry Univac introduced a new lineup that utilized semiconductor memory technology in place of magnetic core memory, accompanied by a revised system naming scheme:

The enhanced 1106 model was redesignated as the UNIVAC 1100/10, with the last digit specifying the count of CPUs or CAUs (for example, a dual-processor 1100/10 was labeled as 1100/12). The updated 1108 became known as the UNIVAC 1100/20.

The upgraded 1110 appeared as the UNIVAC 1100/40, which replaced the Type 7015 64K Plated-Wire Memory cabinet with a new Type 7030 solid-state (static RAM) Memory Cabinet offering 131K capacity. This modification doubled Main Storage from 262K to 524K words. The Type 7030 included eight Memory Modules of 16K (38-bit) each, effectively doubling the module size compared to earlier configurations. Additionally, the Type 7013 131K Core Memory Cabinet was superseded by a Solid-State Memory Cabinet based on Intel’s 1103A DRAM technology.

Released in 1979, the UNIVAC 1100/80 was designed to merge the capabilities of the 1100 and 494 systems. Consistent with previous models, its final digit denoted the number of CAUs installed. This system introduced high-speed cache memory known as the Storage Interface Unit (SIU), which featured an 8K buffer with an optional upgrade to 16K. Positioned between CAU(s)/IOU(s) and slower Main Memory, the SIU initially supported up to two CAUs and IOUs, with later versions expanding capacity to four each. Crucially, the SIU enabled logical partitioning of large multiprocessor environments into separate systems running distinct operating systems.

The CAU executed instructions from both the 36-bit 1100 series and the 30-bit 490 series architectures. It incorporated an Emitter-Coupled Logic (ECL)-based register stack that eliminated parity checking during each read/write operation. Its modular IOU accommodated various Channel Modules tailored for different I/O requirements, including Word Channels for parallel data transfer and Block Multiplexer or Byte Channels optimized for high-speed disk/tape devices or slower peripherals. The SIU contained a BC/7-based minicomputer responsible for microcode loading and diagnostic functions. All units employed ECL technology mounted on multilayer printed circuit boards and were powered by dependable motor/alternator-generated 400 Hz electricity to ensure high reliability and uptime.

A representative top-tier setup—an 1100/84 Multiprocessor featuring four CPUs, two IOUs, two SIUs (each with 16K words), over two million words of Main Memory, maintenance units, power supplies, and consoles—was priced at $5.4 million as of October 1980. Leasing and rental options were available, with customary discounts offered to large-scale or government purchasers.

Also debuting in 1979, the UNIVAC 1100/60 succeeded previous models based on the 1108 and 1106 platforms. Offered in single-processor (1100/61) and dual-processor (1100/62) configurations, it utilized proprietary Sperry-designed microprocessor integrated circuits. Main Storage capacity ranged from 524K up to more than one million words per CPU and featured optional Semiconductor Buffer Storage alongside a modular IOU supporting both Block and Word Channels. A System Support Processor was integrated for diagnostic tasks and console management.

An enhanced dual-processor variant (1100/62 Model E1) included two CPUs equipped with buffer storage, dual IOUs each supporting multiple channel modules, over one million words of Main Storage, support processors, consoles, and maintenance consoles. Priced below $900,000 in early 1980, this system was also available for lease or rental with maintenance contracts; volume purchasers and government entities typically received discounts.

Introduced in 1981, the UNIVAC 1100/70 represented an advancement of the 1100/60 design lineage, effectively replacing earlier systems based on the 1110-derived 1100/40 architecture.

The UNIVAC 1100/90, launched in 1982 as the largest and final model within this series, supported up to four processors and IOUs akin to the capabilities of the 1100/80 but distinguished itself by employing liquid cooling technology.

Additionally, Sperry offered the Integrated Scientific Processor (ISP) as an optional attachment compatible with the 1100/90 system.

SPERRY 2200 series

The UNIVAC brand was phased out by Sperry Corporation in 1983.

Unisys 2200 series

After the 1986 merger between Sperry Corporation and Burroughs Corporation that created Unisys, system designations were updated to reflect the unified company name. While all models shared a common architecture, their capabilities varied across different performance tiers.

These models demonstrate Unisys's ongoing commitment to advancing mainframe platforms, adapting system designs to fulfill evolving enterprise computing requirements.

Unisys ClearPath IX series

In 1996, the company launched the ClearPath IX line, a versatile platform capable of running either the traditional 1100/2200 instruction set (ClearPath IX) or the architecture derived from the Burroughs large systems family (ClearPath NX). The primary distinction between these versions lies in their CPU implementations, which utilize specialized ASICs. Alongside the IX and NX processors, this architecture also incorporated Intel Xeon and briefly, Itanium CPUs. This design approach was intended to ease migration for customers reliant on the older 1100/2200 systems toward more contemporary hardware solutions.

Deployments

A traffic management system implemented in metropolitan Toronto in 1964 linked traffic lights and vehicle detectors to a UNIVAC 1107 computer, enabling automated analysis of traffic flow.

From 1973 until 1981, Sweden operated a national vehicle registration database employing a UNIVAC 1106 front-end combined with UNIVAC 418 units. By March 1979, the installation comprised multiple UNIVAC 1106-II processors with memory expansions, magnetic tape drives, communication controllers connecting police departments and terminals, FASTRAND-III drum storage, front-end UNIVAC 418-II units supporting several hundred CRT and telex terminals, assorted drum and disk storage devices, card readers, and high-speed line printers.

In 1981, this infrastructure was upgraded to a UNIVAC 1100/60 system and subsequently enhanced through later iterations such as UNISYS XPC-L models, reflecting sustained efforts toward technological modernization.

See also

External links

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