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UNIVAC 1101

From Alfawiki
Engineering Research Associates
IndustryComputer hardware
Founded1947
Headquarters
St. Paul, Minnesota
,
United States
ProductsERA 1101 (later UNIVAC 1101), ERA Atlas, ERA 1103, UNIVAC 1103A

The ERA 1101, which was later renamed the UNIVAC 1101, originated as a computer system created by Engineering Research Associates (ERA) in the early 1950s. Following ERA's acquisition by Remington Rand, the system was marketed under the new ownership. The first military variant, known as the ERA Atlas, holds the distinction of being the earliest stored-program computer successfully deployed at a remote location. Remington Rand continued to build upon the 1101's design framework, producing a series of related machines well into the 1960s.

Codebreaking

ERA’s roots trace back to a team of United States Navy cryptanalysts active during World War II. This group developed multiple code-breaking devices aimed at deciphering Japanese communications, paralleling efforts such as the British Colossus computer. After the war, the Navy endorsed maintaining this specialized unit, which subsequently established ERA in St. Paul, Minnesota, operating from repurposed hangars formerly belonging to Chase Aircraft.

As ERA advanced its cryptographic technology, it encountered limitations when enemy codes evolved beyond existing machine capabilities. To address this, they secured Navy funding in 1947 for "Task 13," a project dedicated to creating a fully programmable computer adaptable to changing requirements. The resulting "Atlas" machines incorporated drum memory and a basic integer arithmetic CPU. By December 1950, the first Atlas was completed and installed at the Army Security Agency. An enhanced model featuring both Williams tube memory and drum storage was delivered to the NSA in 1953.

Commercialization

ERA shifted focus toward commercializing their systems. The initial commercial model, originally dubbed "Mabel," was renamed ERA 1101 following Jack Hill’s proposal to reflect the binary representation of 13, corresponding to the project's task number. The ERA 1101 was officially introduced to the public in December 1951. A slightly upgraded Atlas II iteration became known as the ERA 1103, while a more sophisticated successor equipped with core memory and floating point capabilities evolved into the UNIVAC 1103A.

During this timeframe, ERA encountered significant political controversies in Washington, D.C.. Investigative journalist Drew Pearson accused founders Norris and Engstrom of exploiting government connections from wartime for personal benefit, triggering expensive legal disputes that strained both company resources and morale. Amid these challenges, Remington Rand acquired ERA in 1952.

Remington Rand had previously purchased Eckert–Mauchly Computer Corporation, creators of the famous UNIVAC I, recognized as America’s first commercial computer. Although ERA and UNIVAC maintained separate operations initially, Remington Rand rebranded the ERA 1101 as "UNIVAC 1101" to capitalize on UNIVAC’s established market presence. Subsequent models derived from this architecture remained available through the 1960s until eventually being superseded by the distinct UNIVAC 1100 series.

Description

The system measured approximately long by wide and weighed around 16,700 pounds (8.4 short tons) (~8.4 short tons). Its logic circuits comprised about 2700 vacuum tubes. The drum memory featured a diameter of , rotated at 3500 revolutions per minute, included 200 read-write heads, and stored 16,384 words of 24 bits each (roughly equivalent to 48 kB). Memory access times varied between 32 microseconds and 17 milliseconds.

Instructions were encoded in 24 bits: six bits designated for the opcode, four bits specifying a "skip" count (indicating how many memory addresses to bypass), and fourteen bits allocated for addressing memory locations. Data was represented in binary form with negative numbers expressed using ones' complement. Execution times included an addition operation lasting 96 microseconds and multiplication requiring 352 microseconds.

A single 48-bit accumulator functioned using subtractive arithmetic—addition was achieved by subtracting a number’s ones' complement—thereby reducing instances of negative zero. The machine supported a total of thirty-eight instructions.

Instruction Set

Notation
  • y = memory location at address y
  • X = X Register (24-bit)
  • ( ) = value stored at
  • Q = Q Register (24-bit)
  • A = Accumulator (48-bit)
Arithmetic Operations
  • Load (y) into A
  • Load complement of (y) into A
  • Load (y) into A [extended precision]
  • Load complement of (y) into A [extended precision]
  • Load absolute value of (y) into A
  • Load complement of absolute value of (y) into A
  • Add (y) to contents of A
  • Subtract (y) from contents of A
  • Add (y) to A [extended precision]
  • Subtract (y) from A [extended precision]
  • Add absolute value of (y) to contents of A
  • Subtract absolute value of (y) from contents of A
  • Load Q into A
  • Clear lower half of A
  • Add Q to contents of A
  • Transfer contents of A to Q
  • Load [(y) + 1] into A
Multiplication and Division
  • Compute product of Q and (y), store in A
  • Add logical product of Q and (y) to contents of A
  • Compute logical product of Q and (y), store in A
  • Divide contents of A by (y), place quotient in Q and remainder in A
  • Add product of Q and (y) to contents of A
Logical Operations and Control Flow
  • Store lower half of A at address y
  • Shift contents of A left by one position
  • Store Q at address y
  • Shift contents of Q left by one position
  • Replace contents at y with value in A using Q as operator
  • Use contents at y as next instruction address
  • Replace address portion at y with contents of A
  • Use contents at y as next instruction if A is non-zero
  • Load (y) into Q
  • Use contents at y as next instruction if A is negative
  • Use contents at y as next instruction if Q is negative
Input, Output, and Control Commands
  • Output rightmost six digits from memory location (y)
  • Optional halt execution
  • Output and punch rightmost six digits from memory location (y)
  • Intermediate halt execution
  • Final halt execution

See also

External links

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